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公开(公告)号：US20230237965A1
公开(公告)日：2023-07-27
申请号：US18192905
申请日：2023-03-30
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Shinya Ono , Zino Lee , Yun Wang , Fan Gui
IPC: G09G3/3258 , H01L29/786 , H10K59/121
CPC classification number: G09G3/3258 , H01L29/7869 , H10K59/1213 , G09G2300/0842 , G09G2320/0233 , G09G2320/043
Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.
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公开(公告)号：US20230081342A1
公开(公告)日：2023-03-16
申请号：US17859835
申请日：2022-07-07
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Aida R Colon-Berrios , Fan Gui , Levent Erdal Aygun , Mohammad Reza Esmaeili Rad , Ran Tu , Xin Lin , Yun Wang
IPC: G09G3/3233 , H01L27/32
Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor coupled in series with an isolation transistor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations. During a data refresh, the isolation transistor can be turned on to provide current boosting. During emission periods, the isolation transistor is turned off to prevent cathode noise from potentially coupling through to one or more direct-current voltage nodes in the pixel.
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公开(公告)号：US20220180812A1
公开(公告)日：2022-06-09
申请号：US17680059
申请日：2022-02-24
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Shinya Ono , Zino Lee , Yun Wang , Fan Gui
IPC: G09G3/3258 , H01L27/32 , H01L29/786
Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.
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公开(公告)号：US20210255668A1
公开(公告)日：2021-08-19
申请号：US16791905
申请日：2020-02-14
Applicant: Apple Inc.
Inventor： Xiao Xiang , Tong Chen , Fan Gui , Mark T. Winkler , Ran Tu , Tsu-Hui Lin , Wenrui Cai , Yun Wang
Abstract: In some embodiments, a display stack includes a set of light-emitting elements, and a display backplane that includes a set of conductors and is electrically coupled to the set of light-emitting elements. A conductor in the set of conductors has a length, and a curved edge extending along at least a portion of the length. In some embodiments, a display stack includes a set of light-emitting elements; a set of transistors, electrically coupled to the set of light-emitting elements; and a set of conductors, electrically coupled to the set of transistors. The set of transistors may be electrically coupled to the set of conductors at a set of conductive pads. A plurality of conductive pads in the set of conductive pads is coupled to a single conductor in the set of conductors. The single conductor approaches different conductive pads in the plurality of conductive pads at different angles.
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公开(公告)号：US20200251044A1
公开(公告)日：2020-08-06
申请号：US16692933
申请日：2019-11-22
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Fan Gui , Gihoon Choo
Abstract: A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit in the chain of row driver circuits may include a master driver stage, a slave driver stage, and associated control circuitry configured to receive a clock signal and a pulse signal from a preceding row driver in the chain. The master driver stage may be biased using fixed nominal power supply voltages, whereas the slave driver stage may be biased using dynamically adjustable power supply voltages that are optionally reduced relative to that of the nominal power supply voltages. One or more of the master and slave driver stages may be a bootstrapping driver stage having a bootstrapping capacitor.
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Patent Agency Ranking
公开(公告)号：US11651736B2
公开(公告)日：2023-05-16
申请号：US17680059
申请日：2022-02-24
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Shinya Ono , Zino Lee , Yun Wang , Fan Gui
IPC: G09G3/3258 , H01L27/32 , H01L29/786
CPC classification number: G09G3/3258 , H01L27/3262 , H01L29/7869 , G09G2300/0842 , G09G2320/0233 , G09G2320/043
Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.
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公开(公告)号：US11592873B2
公开(公告)日：2023-02-28
申请号：US16791905
申请日：2020-02-14
Applicant: Apple Inc.
Inventor： Xiao Xiang , Tong Chen , Fan Gui , Mark T. Winkler , Ran Tu , Tsu-Hui Lin , Wenrui Cai , Yun Wang
Abstract: In some embodiments, a display stack includes a set of light-emitting elements, and a display backplane that includes a set of conductors and is electrically coupled to the set of light-emitting elements. A conductor in the set of conductors has a length, and a curved edge extending along at least a portion of the length. In some embodiments, a display stack includes a set of light-emitting elements; a set of transistors, electrically coupled to the set of light-emitting elements; and a set of conductors, electrically coupled to the set of transistors. The set of transistors may be electrically coupled to the set of conductors at a set of conductive pads. A plurality of conductive pads in the set of conductive pads is coupled to a single conductor in the set of conductors. The single conductor approaches different conductive pads in the plurality of conductive pads at different angles.
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公开(公告)号：US10923022B2
公开(公告)日：2021-02-16
申请号：US16692933
申请日：2019-11-22
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Fan Gui , Gihoon Choo
Abstract: A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit in the chain of row driver circuits may include a master driver stage, a slave driver stage, and associated control circuitry configured to receive a clock signal and a pulse signal from a preceding row driver in the chain. The master driver stage may be biased using fixed nominal power supply voltages, whereas the slave driver stage may be biased using dynamically adjustable power supply voltages that are optionally reduced relative to that of the nominal power supply voltages. One or more of the master and slave driver stages may be a bootstrapping driver stage having a bootstrapping capacitor.
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公开(公告)号：US10916198B2
公开(公告)日：2021-02-09
申请号：US16716911
申请日：2019-12-17
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Shinya Ono , Zino Lee , Yun Wang , Fan Gui
IPC: G09G3/3258 , H01L27/32 , H01L29/786
Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.
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公开(公告)号：US20210020109A1
公开(公告)日：2021-01-21
申请号：US17062786
申请日：2020-10-05
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Shinya Ono , Zino Lee , Yun Wang , Fan Gui
IPC: G09G3/3258 , H01L27/32 , H01L29/786
Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.
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