公开(公告)号：US11348533B1

公开(公告)日：2022-05-31

申请号：US16864241

申请日：2020-05-01

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Gihoon Choo ,  Shiping Shen ,  Jie Won Ryu ,  Zino Lee ,  Hassan Edrees ,  Ting-Kuo Chang

IPC: G09G3/3266

Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The thin-film transistors may be controlled using at least first and second horizontal scan line signals. Loading different data values into any given row in the array may cause the scan line signals to exhibit varying rise/fall times, which results in horizontal crosstalk and luminance non-uniformity across the display. The rise and fall times of the second scan line signal are crucial, so the second scan line signal is driven by two separate scan line drivers formed on both sides of the display. Only the fall time of the first scan line signal is crucial, so the first scan line signal is driven by only one peripheral scan line driver and is coupled to an auxiliary pull-down circuit that is only activated during the pull-down transition.

公开(公告)号：US11049457B1

公开(公告)日：2021-06-29

申请号：US16852234

申请日：2020-04-17

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Chun-Chieh Lin ,  Gihoon Choo ,  Hassan Edrees ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to a drive transistor and other associated thin-film transistors. The array may be grouped into column pairs, where each column pair includes a first pixel column and a second pixel column that is mirrored with respect to the first pixel column. The drive transistors within each column pair may be formed towards the center of that column pair, whereas the data lines associated with that column pair may be formed along the outer peripheral edges of that column pair. Configured in this way, parasitic coupling between the data lines and any sensitive/floating nodes of the drive transistor may be substantially reduced, which mitigates pixel column crosstalk and ensures luminance uniformity across the display.

公开(公告)号：US20200251044A1

公开(公告)日：2020-08-06

申请号：US16692933

申请日：2019-11-22

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Fan Gui ,  Gihoon Choo

IPC: G09G3/296 ,  H03K19/00

Abstract: A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit in the chain of row driver circuits may include a master driver stage, a slave driver stage, and associated control circuitry configured to receive a clock signal and a pulse signal from a preceding row driver in the chain. The master driver stage may be biased using fixed nominal power supply voltages, whereas the slave driver stage may be biased using dynamically adjustable power supply voltages that are optionally reduced relative to that of the nominal power supply voltages. One or more of the master and slave driver stages may be a bootstrapping driver stage having a bootstrapping capacitor.

公开(公告)号：US11922887B1

公开(公告)日：2024-03-05

申请号：US17368472

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chuan-Jung Lin ,  Gihoon Choo ,  Hassan Edrees ,  Hei Kam ,  Jung Yen Huang ,  Pei-En Chang ,  Rungrot Kitsomboonloha ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3275 ,  H10K59/121 ,  H10K59/126 ,  H10K59/131

CPC classification number: G09G3/3275 ,  H10K59/1213 ,  H10K59/1216 ,  H10K59/126 ,  H10K59/131 ,  G09G2320/0214

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

公开(公告)号：US20230014107A1

公开(公告)日：2023-01-19

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US11211020B2

公开(公告)日：2021-12-28

申请号：US16369319

申请日：2019-03-29

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Zino Lee ,  Gihoon Choo ,  Hassan Edrees ,  Chin-Wei Lin

IPC: G09G3/36 ,  G09G3/3225 ,  G09G3/3291 ,  G09G3/3233 ,  G09G3/3266

Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

公开(公告)号：US20250008799A1

公开(公告)日：2025-01-02

申请号：US18667776

申请日：2024-05-17

Applicant: Apple Inc.

Inventor： Shyuan Yang ,  Abbas Jamshidi Roudbari ,  Gihoon Choo ,  Jae Won Choi ,  Jean-Pierre S. Guillou ,  Jonglo Park ,  Kyounghwan Kim ,  Ricardo A. Peterson ,  Sungki Lee ,  Ting-Kuo Chang ,  Tsung-Ting Tsai ,  Warren S. Rieutort-Louis ,  Yi Qiao ,  Yuchi Che ,  Yue Cui ,  Yue Jack Chu ,  Zhizhen Ma

IPC: H10K59/131 ,  H10K59/121 ,  H10K59/65

Abstract: A display may include an active area with a first region and a second region. The first region may overlap an input-output component such as a camera and may have a higher transparency than the second region. The first region may have a lower pixel density than the second region. Signal lines that pass through the first region may have transparent portions that overlap the first region and opaque portions that overlap the second region. To mitigate artifacts caused by high resistance of the transparent portions of the signal lines, the signal lines may include supplemental opaque portions that are electrically connected in parallel to the transparent portions and that are routed through the second region around the first region.

公开(公告)号：US20240038154A1

公开(公告)日：2024-02-01

申请号：US18355342

申请日：2023-07-19

Applicant: Apple Inc.

Inventor： Jie Won Ryu ,  Ing-Jye Wang ,  Alex H Pai ,  Alexandre V Gauthier ,  Ardra Singh ,  Arthur L Spence ,  Gihoon Choo ,  Hyunsoo Kim ,  Hyunwoo Nho ,  Jenny Hu ,  Graeme M Williams ,  Jongyup Lim ,  Kingsuk Brahma ,  Marc J DeVincentis ,  Peter F Holland ,  Shawn P Hurley

IPC: G09G3/3208

CPC classification number: G09G3/3208 ,  G09G2340/0435 ,  G09G2320/0266 ,  G09G2320/0626 ,  G09G2310/08

Abstract: An electronic device may include processing circuitry configured to generate a first frame of image content and a second frame of image content. The second frame of image content is different from the first frame of image content. The electronic device may also include a display configured to display the first frame of image content at a first refresh rate. In response to receiving the second frame of image content, the electronic device may initially increase the refresh rate before tapering back to the first refresh rate while displaying the second frame of image content.

公开(公告)号：US11580905B2

公开(公告)日：2023-02-14

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US20220181418A1

公开(公告)日：2022-06-09

申请号：US17504230

申请日：2021-10-18

Applicant: Apple Inc.

Inventor： Jung Yen Huang ,  Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Cheng Min Hu ,  Chih Pang Chang ,  Ching-Sang Chuang ,  Gihoon Choo ,  Jiun-Jye Chang ,  Po-Chun Yeh ,  Shih Chang Chang ,  Yu-Wen Liu ,  Zino Lee

IPC: H01L27/32 ,  H01L29/786 ,  H01L29/66

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.