公开(公告)号：US10410314B2

公开(公告)日：2019-09-10

申请号：US15499561

申请日：2017-04-27

Applicant: Apple Inc.

Inventor： Jaewon Shin

IPC: G06T1/20 ,  G06T3/40 ,  G06T5/50 ,  G06T3/00

Abstract: A cross fader circuit that receives first raw image data and second raw image data and outputs blended raw image data. The cross fader circuit includes a first scaling circuit, a second scaling circuit, and an alpha blender. The first scaling circuit downscales first raw image data captured by a first sensor with a first field of view to match a size of a blending window. The second scaling circuit upscales second raw image data to match the size of a canvas window that encloses the blending window. The second raw image data may be a cropped version of raw image data captured by a second sensor of a second field of view wider than the first field of view. An alpha blender circuit generates a blended raw image data matching the size of the canvas window from the downscaled first raw image data and upscaled second raw image data.

公开(公告)号：US20180315156A1

公开(公告)日：2018-11-01

申请号：US15499561

申请日：2017-04-27

Applicant: Apple Inc.

Inventor： Jaewon Shin

IPC: G06T1/20 ,  G06T3/40 ,  G06T5/50

CPC classification number: G06T1/20 ,  G06T3/00 ,  G06T3/40 ,  G06T5/50 ,  G06T2207/20221 ,  G06T2210/22

Abstract: A cross fader circuit that receives first raw image data and second raw image data and outputs blended raw image data. The cross fader circuit includes a first scaling circuit, a second scaling circuit, and an alpha blender. The first scaling circuit downscales first raw image data captured by a first sensor with a first field of view to match a size of a blending window. The second scaling circuit upscales second raw image data to match the size of a canvas window that encloses the blending window. The second raw image data may be a cropped version of raw image data captured by a second sensor of a second field of view wider than the first field of view. An alpha blender circuit generates a blended raw image data matching the size of the canvas window from the downscaled first raw image data and upscaled second raw image data.

公开(公告)号：US20240265233A1

公开(公告)日：2024-08-08

申请号：US18614256

申请日：2024-03-22

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20230099652A1

公开(公告)日：2023-03-30

申请号：US17991373

申请日：2022-11-21

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20190340491A1

公开(公告)日：2019-11-07

申请号：US15971882

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Erik K. Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06N3/08 ,  G06F1/32

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20180007241A1

公开(公告)日：2018-01-04

申请号：US15198363

申请日：2016-06-30

Applicant: Apple Inc.

Inventor： D. Amnon Silverstein ,  Jaewon Shin

IPC: H04N5/217 ,  G06T5/00 ,  G06T7/00 ,  G06T1/20 ,  G06T5/20 ,  G06T3/40

CPC classification number: H04N5/2176 ,  G06T1/20 ,  G06T3/4015 ,  G06T5/002 ,  G06T5/20 ,  G06T7/0002 ,  G06T2207/10024 ,  G06T2207/20024 ,  H04N5/3675 ,  H04N9/045 ,  H04N2209/045 ,  H04N2209/046

Abstract: Embodiments of the present disclosure relate to a sensor interface circuit that performs scaling of image data in a Bayer pattern without spreading defective pixels across multiple pixels. The sensor interface circuit may include a register circuit storing operating parameters of the sensor interface circuit. The sensor interface circuit includes a scaling circuit with a first defect pixel detection circuit to detect a first defective pixel in an input image by analyzing pixels in a line of an input image data along a first direction. A first scaling circuit is coupled to the first defect pixel detection circuit and generates a scaled line of pixels representing the line of the input image scaled along the first direction according to the operating parameters.

公开(公告)号：US09860429B1

公开(公告)日：2018-01-02

申请号：US15198363

申请日：2016-06-30

Applicant: Apple Inc.

Inventor： D. Amnon Silverstein ,  Jaewon Shin

IPC: H04N5/225 ,  H04N5/217 ,  G06T7/00 ,  G06T3/40 ,  G06T1/20 ,  G06T5/00 ,  G06T5/20

CPC classification number: H04N5/2176 ,  G06T1/20 ,  G06T3/4015 ,  G06T5/002 ,  G06T5/20 ,  G06T7/0002 ,  G06T2207/10024 ,  G06T2207/20024 ,  H04N5/3675 ,  H04N9/045 ,  H04N2209/045 ,  H04N2209/046

Abstract: Embodiments of the present disclosure relate to a sensor interface circuit that performs scaling of image data in a Bayer pattern without spreading defective pixels across multiple pixels. The sensor interface circuit may include a register circuit storing operating parameters of the sensor interface circuit. The sensor interface circuit includes a scaling circuit with a first defect pixel detection circuit to detect a first defective pixel in an input image by analyzing pixels in a line of an input image data along a first direction. A first scaling circuit is coupled to the first defect pixel detection circuit and generates a scaled line of pixels representing the line of the input image scaled along the first direction according to the operating parameters.