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    PATCH WARPER CIRCUIT FOR IMAGE PROCESSING
    1.
    发明申请
    PATCH WARPER CIRCUIT FOR IMAGE PROCESSING 审中-公开

    公开(公告)号：US20180315164A1

    公开(公告)日：2018-11-01

    申请号：US15499755

    申请日：2017-04-27

    Applicant: Apple Inc.

    Inventor： Jaewon Shin

    IPC: G06T3/40 ,  G06T3/00

    CPC classification number: G06T3/4015 ,  G06T3/0093 ,  G06T3/4007

    Abstract: Embodiments relate to a patch processor that warps patches of input image data. The patch processor includes a patch direct memory access (DMA) circuit that obtains the patches via direct memory access. The patch processor includes a patch warper circuit that generates warped patches by processing the patches by performing interpolation in a raster scan fashion using a set of coordinates, for example. The patch warper circuit may also process pixels of the patches using an adder or subtractor circuit. In addition, the patch warper circuit may interleave warped patches of different image channels such as RGB or YCbCr colors. The patch warper circuit can also double-buffer the patches and warped patches.

    Scalable neural network processing engine
    2.
    发明授权
    Scalable neural network processing engine 有权

    公开(公告)号：US11989640B2

    公开(公告)日：2024-05-21

    申请号：US17991373

    申请日：2022-11-21

    Applicant: Apple Inc.

    Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

    IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

    CPC classification number: G06N3/04 ,  G06F1/3296 ,  G06N3/08

    Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

    Scalable neural network processing engine
    3.
    发明授权
    Scalable neural network processing engine 有权

    公开(公告)号：US11537838B2

    公开(公告)日：2022-12-27

    申请号：US15971882

    申请日：2018-05-04

    Applicant: Apple Inc.

    Inventor： Erik K. Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

    IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

    Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

    NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS
    5.
    发明公开
    NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS 审中-公开

    公开(公告)号：US20240329933A1

    公开(公告)日：2024-10-03

    申请号：US18127650

    申请日：2023-03-28

    Applicant: Apple Inc.

    Inventor： Lei Wang ,  Jaewon Shin ,  Seungjin Lee ,  Ji Liang Song ,  Michael L. Liu ,  Christopher L. Mills

    IPC: G06F7/544 ,  G06N3/063

    CPC classification number: G06F7/5443 ,  G06N3/063

    Abstract: Embodiments of the present disclosure relate to a multiply-accumulator circuit that includes a main multiplier circuit operable in a floating-point mode or an integer mode and a supplemental multiplier circuit that operates in the integer mode. The main multiplier circuit generates a multiplied output that undergoes subsequent operations including a shifting operation in the floating-point mode whereas the supplemental multiplier generates another multiplied output that does not undergo any shifting operations. Hence, in the integer mode, two parallel multiply-add operations may be performed by the two multiplier circuits, and therefore accelerate the multiply-adder operations. Due to the lack of additional shifters associated with the supplemental multiplier circuit, the multiply-accumulator circuit does not have a significantly increased footprint.

    Patch warper circuit for image processing
    6.
    发明授权
    Patch warper circuit for image processing 有权

    公开(公告)号：US10249023B2

    公开(公告)日：2019-04-02

    申请号：US15499755

    申请日：2017-04-27

    Applicant: Apple Inc.

    Inventor： Jaewon Shin

    IPC: G06T3/00 ,  G06T3/40

    Abstract: Embodiments relate to a patch processor that warps patches of input image data. The patch processor includes a patch direct memory access (DMA) circuit that obtains the patches via direct memory access. The patch processor includes a patch warper circuit that generates warped patches by processing the patches by performing interpolation in a raster scan fashion using a set of coordinates, for example. The patch warper circuit may also process pixels of the patches using an adder or subtractor circuit. In addition, the patch warper circuit may interleave warped patches of different image channels such as RGB or YCbCr colors. The patch warper circuit can also double-buffer the patches and warped patches.

    CACHE PREFETCH FOR NEURAL PROCESSOR CIRCUIT
    9.
    发明公开
    CACHE PREFETCH FOR NEURAL PROCESSOR CIRCUIT 审中-公开

    公开(公告)号：US20230289291A1

    公开(公告)日：2023-09-14

    申请号：US17691609

    申请日：2022-03-10

    Applicant: Apple Inc.

    Inventor： Seungjin Lee ,  Jaewon Shin ,  Christopher L Mills

    IPC: G06F12/0862

    CPC classification number: G06F12/0862 ,  G06F2212/602

    Abstract: A neural processor may include a system memory access circuit coupled to a system memory. The system memory access circuit is configured to fetch, from the system memory, first input data of a first task associated with a neural network. The neural processor may also include neural engines coupled to the system memory access circuit. The neural engines are configured to perform convolution operations on the first input data in a first set of operating cycles. The neural processor may further include a cache access circuit coupled to a cache. The cache access circuit is configured to instruct the cache to prefetch from the system memory, during the first set of operating cycles corresponding to the first task, second input data of a second task of the neural network. The second task is scheduled for processing in a second set of operating cycles after the first set of operating cycles.

    Configurable histogram-of-oriented gradients (HOG) processor
    10.
    发明授权
    Configurable histogram-of-oriented gradients (HOG) processor 有权

    公开(公告)号：US10586128B2

    公开(公告)日：2020-03-10

    申请号：US15954103

    申请日：2018-04-16

    Applicant: Apple Inc.

    Inventor： Suk Hwan Lim ,  Jaewon Shin

    IPC: G06K9/00 ,  G06K9/62 ,  G06K9/46

    Abstract: Embodiments relate to a histogram-of-oriented gradients (HOG) module. The HOG module is implemented in hardware rather than software. The HOG module applies an algorithm to an image to identify gradient orientation in localized portions of the image. The HOG module creates a histogram-of orientation gradients based on the identified gradient orientations.

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