公开(公告)号：US11740993B2

公开(公告)日：2023-08-29

申请号：US17538939

申请日：2021-11-30

Applicant: Apple Inc.

Inventor： Andrew J. Beaumont-Smith ,  Sandeep Gupta ,  Krishna C. Potnuru ,  Matthias Knoth

IPC: G06F12/00 ,  G06F11/34 ,  G06F11/30 ,  G06F12/02

CPC classification number: G06F11/348 ,  G06F11/3037 ,  G06F12/0223 ,  G06F2212/1008

Abstract: An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of processor circuits, to monitor memory requests transmitted between ones of the plurality of processor circuits and the cache memory circuit, and then to select a particular memory request of monitored memory requests using an arbitration algorithm. The trace control circuit may be further configured to allocate space in a trace buffer to the particular memory request, and to store, in the trace buffer, information associated with the particular memory request.

公开(公告)号：US20220091649A1

公开(公告)日：2022-03-24

申请号：US17026121

申请日：2020-09-18

Applicant: Apple Inc.

Inventor： Matthias Knoth ,  Srikanth Balasubramanian ,  Venkatram Krishnaswamy ,  Ramesh B. Gunna

IPC: G06F1/28 ,  G06F1/3228 ,  G06Q50/06

Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.

公开(公告)号：US10859628B2

公开(公告)日：2020-12-08

申请号：US16375344

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

IPC: G01R31/317 ,  G01R19/00 ,  H03M1/12 ,  G01R31/3177

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

公开(公告)号：US12182003B1

公开(公告)日：2024-12-31

申请号：US17647539

申请日：2022-01-10

Applicant: Apple Inc.

Inventor： Jaidev P. Patwardhan ,  Matthias Knoth ,  Shekhar S. Srikantaiah ,  Prakhar Malhotra ,  Matthew C. Widmann ,  Dmitriy B. Solomonov ,  Constantin Pistol

IPC: G06F11/36 ,  G06F11/07

Abstract: An apparatus includes a processor circuit that includes a memory circuit, one or more processor cores, and a debug circuit. The debug circuit may be configured, in response to activation of a trace mode to record information indicative of instructions executing on the one or more processor cores, to write a trace data stream to the memory circuit that includes trace data collected on the instructions executing on the one or more processor cores. In response to a particular instruction within one of the processor cores specifying a write of a data value to an architecturally visible trace register, the debug circuit may be further configured to output the data value to the trace data stream as part of executing the particular instruction.

公开(公告)号：US11347198B2

公开(公告)日：2022-05-31

申请号：US17012611

申请日：2020-09-04

Applicant: Apple Inc.

Inventor： Matthias Knoth ,  Ramesh B. Gunna ,  Srikanth Balasubramanian

IPC: H03M1/06 ,  G05B19/406 ,  H03M1/12 ,  H03M1/46 ,  H04W52/36 ,  G01K3/00 ,  G01K15/00

Abstract: Systems, apparatuses, and methods for implementing an optimized adaptive thermal control mechanism for an integrated circuit (IC) are described. A control unit receives a digital input value which is representative of a temperature of an IC. The control unit compares the input value to at least two set points. A result of a first comparison determines whether an accumulator is incremented or decremented by a programmable gain value. A result of a second comparison determines whether the accumulator is primed with a preset ramp-up value. The preset ramp-up value is used since the accumulator can take several sensing cycles to reach the optimal control value while thermal gradients can become critical in only a few cycles. The output of the accumulator is provided to an actuator which adjusts parameter(s) to modulate the IC's temperature. The granularity and range of the accumulator matches the granularity and range of the actuator.

公开(公告)号：US10054618B2

公开(公告)日：2018-08-21

申请号：US14829392

申请日：2015-08-18

Applicant: Apple Inc.

Inventor： Matthias Knoth ,  Conrad H. Ziesler ,  Toshinari Takayanagi

IPC: H01L29/10 ,  H01L21/66 ,  G01R19/25 ,  G01R19/00

CPC classification number: G01R19/2509 ,  G01R19/0084 ,  G06F1/30 ,  G06F11/00 ,  G06F11/3058

Abstract: In an embodiment, an integrated circuit includes a first circuit and a characterization circuit to capture a histogram of the supply voltage magnitude to the first circuit (or other characteristics of the first circuit). In various embodiments, the characterization circuit may: be located near the first circuit; include a sample/hold circuit that may sample the supply voltage in a short window of time and an ADC that is configured to converge to the sampled voltage over multiple orders of magnitude longer than the short window; be relatively small and low power; capture multiple histograms, e.g. one for each mode of the first circuit; support a blackout interval during mode changes; support a zoom feature to a subrange of supply voltage disabled with fine-grain histogram buckets; and/or include one or more comparators to detect maximum and/or minimum voltages experienced over a time interval.