公开(公告)号：US10859628B2

公开(公告)日：2020-12-08

申请号：US16375344

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

IPC: G01R31/317 ,  G01R19/00 ,  H03M1/12 ,  G01R31/3177

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

公开(公告)号：US09892802B1

公开(公告)日：2018-02-13

申请号：US14714381

申请日：2015-05-18

Applicant: Apple Inc.

Inventor： Bo Yang ,  Andrew J. Copperhall ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/10 ,  G01R31/3177 ,  G11C29/50

CPC classification number: G11C29/10 ,  G01R31/3177

Abstract: A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.

公开(公告)号：US20160091564A1

公开(公告)日：2016-03-31

申请号：US14502284

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Bibo Li ,  Andrew J. Copperhall ,  Bo Yang

IPC: G01R31/3177

CPC classification number: G01R31/318566 ,  G01R31/318544

Abstract: Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.

Abstract translation: 公开了与测试设备有关的技术。 在一个实施例中，一种方法包括从被测设备（DUT）的第一测试接收故障信息。 在该实施例中，DUT包括多个扫描链，每条扫描链包括多个扫描单元。 在该实施例中，第一测试基于第一压缩测试图案。 在本实施例中，故障信息不能确定哪个扫描单元是故障扫描单元。 在该实施例中，该方法包括基于第一压缩测试图案生成多个压缩测试图案。 在该实施例中，多个压缩测试图案指定一对一模式。 在该实施例中，该方法包括使用多个压缩测试模式来执行DUT的一个或多个第二测试，以确定确定一个或多个故障扫描单元。

公开(公告)号：US20200319248A1

公开(公告)日：2020-10-08

申请号：US16375344

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

IPC: G01R31/317 ,  G01R19/00 ,  G01R31/3177 ,  H03M1/12

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

公开(公告)号：US20170084349A1

公开(公告)日：2017-03-23

申请号：US15369670

申请日：2016-12-05

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/12 ,  G11C8/00 ,  G11C7/00

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

公开(公告)号：US10026499B2

公开(公告)日：2018-07-17

申请号：US15369670

申请日：2016-12-05

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C7/10 ,  G11C29/08 ,  G11C8/06 ,  G11C11/4093 ,  G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C7/00 ,  G11C8/00 ,  G11C29/56

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

公开(公告)号：US09514842B2

公开(公告)日：2016-12-06

申请号：US14495506

申请日：2014-09-24

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C7/10 ,  G11C29/08 ,  G11C8/06 ,  G11C11/4093 ,  G11C29/12 ,  G11C29/02 ,  G11C29/14 ,  G11C29/56

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract translation: 公开了与记忆测试相关的技术。 在一个实施例中，公开了一种集成电路，其包括存储器和接口电路。 接口电路被配置为从内置的自检（BIST）单元接收一个或多个测试信号。 接口电路还被配置为独立于一个或多个测试信号接收来自自动测试设备（ATE）的一个或多个配置信号。 接口电路还被配置为基于一个或多个测试信号并且基于一个或多个配置信号向存储器发出一个或多个指令信号。 在一些实施例中，接口电路被配置为使得BIST单元能够检测BIST单元不被设计用于测试的功能中的错误。

公开(公告)号：US09519026B2

公开(公告)日：2016-12-13

申请号：US14502284

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Bibo Li ,  Andrew J. Copperhall ,  Bo Yang

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318566 ,  G01R31/318544

Abstract: Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.

Abstract translation: 公开了与测试设备有关的技术。 在一个实施例中，一种方法包括从被测设备（DUT）的第一测试接收故障信息。 在该实施例中，DUT包括多个扫描链，每条扫描链包括多个扫描单元。 在该实施例中，第一测试基于第一压缩测试图案。 在本实施例中，故障信息不能确定哪个扫描单元是故障扫描单元。 在该实施例中，该方法包括基于第一压缩测试图案生成多个压缩测试图案。 在该实施例中，多个压缩测试模式指定一对一模式。 在该实施例中，该方法包括使用多个压缩测试模式来执行DUT的一个或多个第二测试，以确定确定一个或多个故障扫描单元。

公开(公告)号：US20160086678A1

公开(公告)日：2016-03-24

申请号：US14495506

申请日：2014-09-24

Applicant: Apple Inc.

Inventor： Dragos F. Botea ,  Bibo Li ,  Vijay M. Bettada

IPC: G11C29/12

CPC classification number: G11C29/12 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C29/021 ,  G11C29/08 ,  G11C29/14 ,  G11C2029/5602

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract translation: 公开了与记忆测试相关的技术。 在一个实施例中，公开了一种集成电路，其包括存储器和接口电路。 接口电路被配置为从内置的自检（BIST）单元接收一个或多个测试信号。 接口电路还被配置为独立于一个或多个测试信号接收来自自动测试设备（ATE）的一个或多个配置信号。 接口电路还被配置为基于一个或多个测试信号并且基于一个或多个配置信号向存储器发出一个或多个指令信号。 在一些实施例中，接口电路被配置为使得BIST单元能够检测BIST单元不被设计用于测试的功能中的错误。