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公开(公告)号:US12207512B2
公开(公告)日:2025-01-21
申请号:US18513132
申请日:2023-11-17
Applicant: Apple Inc.
Inventor: Cheng-Ho Yu , Chin-Wei Lin , Shyuan Yang , Ting-Kuo Chang , Tsung-Ting Tsai , Warren S. Rieutort-Louis , Shih-Chang Chang , Yu Cheng Chen , John Z. Zhong
IPC: H10K59/131 , G06F3/044 , G09G3/3233 , G09G3/3266 , H10K59/10 , H10K59/40 , H10K59/88
Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
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公开(公告)号:US20240065057A1
公开(公告)日:2024-02-22
申请号:US18328427
申请日:2023-06-02
Applicant: Apple Inc.
Inventor: Shin-Hung Yeh , Abbas Jamshidi Roudbari , Chien-Ya Lee , I-Cheng Shih , Shyuan Yang , Tsung-Ting Tsai
IPC: H10K59/131 , H10K59/126 , H10K59/121
CPC classification number: H10K59/131 , H10K59/126 , H10K59/1213
Abstract: A display may include pixels arranged in rows and columns in an active area and display driver circuitry in an inactive area. Data lines for the pixels may be positioned in the active area. Fanout lines may be routed through the active area. Each fanout line may electrically connect the display driver circuitry to a respective data line. One or more pixels may include a drive transistor and a light-emitting diode that are connected in series between a first power supply terminal and a second power supply terminal. A conductive layer may form a first terminal (such as the source terminal, the gate terminal, or the drain terminal) for the drive transistor. A conductive shielding layer may be interposed between the conductive layer and a fanout line to mitigate capacitive coupling between the terminal of the drive transistor and the fanout line.
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公开(公告)号:US11823621B2
公开(公告)日:2023-11-21
申请号:US17576619
申请日:2022-01-14
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Shyuan Yang , Chuang Qian , Abbas Jamshidi Roudbari , Ting-Kuo Chang
IPC: G09G3/32 , G09G3/3225 , G09G3/3233
CPC classification number: G09G3/3225 , G09G3/3233 , G09G2300/043 , G09G2300/0417 , G09G2300/0819 , G09G2300/0861 , G09G2310/0262 , G09G2310/0297 , G09G2310/06 , G09G2310/061 , G09G2320/0214 , G09G2320/0242 , G09G2320/0247 , G09G2320/0252 , G09G2320/043 , G09G2320/045 , G09G2320/064 , G09G2340/0435
Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.
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公开(公告)号:US10896642B1
公开(公告)日:2021-01-19
申请号:US16828052
申请日:2020-03-24
Applicant: Apple Inc.
Inventor: Chuang Qian , Tsung-Ting Tsai , Shyuan Yang , Cheng-Chih Hsieh , Abbas Jamshidi Roudbari , Ting-Kuo Chang , Shih-Chang Chang
IPC: G09G3/3233 , G09G3/3266 , G09G3/3275 , G11C19/28
Abstract: Electronic devices may include displays having organic light-emitting diode pixels, display driver circuitry, and gate driver circuitry. To reduce the amount of space occupied in the inactive area of a display by the gate driver circuitry, one or more of the shift registers in the gate driver circuitry may include register circuits that are shared by multiple rows of pixels. Different drivers may use different clock frequencies to ensure synchronous operation of the display even when some register circuits share pixel rows. For increased flexibility in the arrangement of the register circuits in the shift registers, one or more of the shift registers may be split across the active area of the display. In some cases, one of the emission drivers may be omitted from the gate driver circuitry and a single emission driver may provide multiple emission control signals for the pixels.
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公开(公告)号:US10573229B2
公开(公告)日:2020-02-25
申请号:US16425604
申请日:2019-05-29
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Hung Sheng Lin , Vasudha Gupta , Shinya Ono , Tsung-Ting Tsai , Shyuan Yang
IPC: G09G3/32 , G09G3/3233 , G09G3/3291
Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.
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公开(公告)号:US10438540B2
公开(公告)日:2019-10-08
申请号:US15701342
申请日:2017-09-11
Applicant: Apple Inc.
Inventor: Shyuan Yang , Abbas Jamshidi Roudbari , Ting-Kuo Chang , Tsung-Ting Tsai , Warren S. Rieutort-Louis
IPC: G09G3/3266 , G09G3/3225 , G09G3/20
Abstract: Aspects of the subject technology relate to display circuitry. The display circuitry includes gate-in-panel (GIP) control circuitry on opposing sides of a display pixel array. The GIP control circuitry can include scan drivers for each pixel row on both sides of that pixel row, the scan drivers on either side configured for enablement or disablement for single-sided reduced-power operations. The GIP control circuitry can include a single scan driver and a single emission controller for each pixel row, in which the scan driver and emission controller for each row are disposed on opposing sides of the row. The scan drivers for a first subset of the pixel rows can be interleaved with the emission controllers for a different subset of the pixel rows.
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公开(公告)号:US20190279559A1
公开(公告)日:2019-09-12
申请号:US16425604
申请日:2019-05-29
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Hung Sheng Lin , Vasudha Gupta , Shinya Ono , Tsung-Ting Tsai , Shyuan Yang
IPC: G09G3/32 , G09G3/3233 , G09G3/3291
Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.
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公开(公告)号:US20190237010A1
公开(公告)日:2019-08-01
申请号:US16379323
申请日:2019-04-09
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Shyuan Yang , Chuang Qian , Abbas Jamshidi Roudbari , Ting-Kuo Chang
IPC: G09G3/3225 , G09G3/3233
Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.
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公开(公告)号:US20190088208A1
公开(公告)日:2019-03-21
申请号:US16120076
申请日:2018-08-31
Applicant: Apple Inc.
Inventor: Ting-Kuo Chang , Abbas Jamshidi Roudbari , Tsung-Ting Tsai , Warren S. Rieutort-Louis , Shinya Ono , Shin-Hung Yeh , Chien-Ya Lee , Shyuan Yang
IPC: G09G3/3275 , G09G3/3233 , G09G3/3266
Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.
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公开(公告)号:US20190057646A1
公开(公告)日:2019-02-21
申请号:US15996366
申请日:2018-06-01
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Shyuan Yang , Chuang Qian , Abbas Jamshidi Roudbari , Ting-Kuo Chang
IPC: G09G3/3225
Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.
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