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公开(公告)号：US10969993B2
公开(公告)日：2021-04-06
申请号：US16521723
申请日：2019-07-25
Applicant: Arm Limited
Inventor： Andrew John Turner , Alex James Waugh , Geoffray Lacourba , Fergus Wilson MacGarry
Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.
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公开(公告)号：US09430421B2
公开(公告)日：2016-08-30
申请号：US14206236
申请日：2014-03-12
Applicant: ARM Limited
CPC classification number: G06F13/26
Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.
Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。
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