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公开(公告)号：US10891084B2
公开(公告)日：2021-01-12
申请号：US16353257
申请日：2019-03-14
Applicant: Arm Limited
Inventor： Alex James Waugh , Geoffray Mattheiu Lacourba , Andrew John Turner , Sergio Schuler
IPC: G06F3/06 , G06F9/50 , G06F13/16 , G06F12/0837 , G06F9/54
Abstract: Aspects of the present disclosure relate to an interconnect comprising an interface to couple to a master device, the interface comprising buffer storage. The interface is configured to receive a request from the master device for data comprising a plurality of data blocks, the master device requiring the data blocks in a defined order. A data collator is configured to: receive the request; issue a data pull request to cause the interface to allocate buffer space in the buffer storage for buffering the requested data; and responsive to receiving a confirmation that the buffer space is allocated, provide the requested data to the buffer storage. The interface is configured to employ the buffer storage to enable re-ordering of the plurality of data blocks of the requested data, prior to outputting the plurality of data blocks to the master device; and output the plurality of data blocks to the master device in the defined order.
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公开(公告)号：US09378162B2
公开(公告)日：2016-06-28
申请号：US13898816
申请日：2013-05-21
Applicant: ARM LIMITED
Inventor： Anthony Jebson , Andrew John Turner , Matthew Lucien Evans , Gareth James Evans , Adam James McNeeney
CPC classification number: G06F13/24 , G06F9/45533 , G06F9/4812
Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.
Abstract translation: 一种中断控制器，用于控制在包括至少一个物理处理单元的数据处理装置处接收的中断的路由和处理，所述物理处理单元被配置为运行多个虚拟处理器和存储器中的至少一个。 中断控制器包括具有与单元对应的至少一个数据存储器的再分配电路，数据存储器存储指向虚拟挂起表的指针，该虚拟挂起表存储当前在相应单元上运行的虚拟处理器的当前待处理的虚拟中断，以及指向待处理表的指针 被配置为存储用于相应单元的当前待处理的物理中断，以及被配置为接收用于中断虚拟处理器的虚拟中断的输入。 控制电路被配置为将虚拟中断添加到虚拟挂起表并将虚拟中断存储在存储在存储器中的虚拟处理器的虚拟挂起表中。
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公开(公告)号：US11429426B2
公开(公告)日：2022-08-30
申请号：US17056896
申请日：2019-05-01
Applicant: Arm Limited
Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.
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公开(公告)号：US11269773B2
公开(公告)日：2022-03-08
申请号：US16595863
申请日：2019-10-08
Applicant: Arm Limited
Inventor： Bruce James Mathewson , Phanindra Kumar Mannava , Jamshed Jalal , Klas Magnus Bruce , Andrew John Turner
IPC: G06F9/52 , G06F9/30 , G06F15/78 , G06F13/42 , G06F13/16 , G06F12/0831 , G06F12/0817 , G06F12/0815
Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.
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公开(公告)号：US12174753B2
公开(公告)日：2024-12-24
申请号：US18253621
申请日：2021-11-18
Applicant: Arm Limited
Inventor： Joseph Michael Pusdesris , Klas Magnus Bruce , Jamshed Jalal , Dimitrios Kaseridis , Gurunath Ramagiri , Ho-Seop Kim , Andrew John Turner , Rania Hussein Hassan Mameesh
IPC: G06F12/126 , G06F12/0811
Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.
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Patent Agency Ranking
公开(公告)号：US11777869B2
公开(公告)日：2023-10-03
申请号：US16170366
申请日：2018-10-25
Applicant: Arm Limited
Inventor： Fergus Wilson MacGarry , Alex James Waugh , Andrew John Turner
IPC: H04B10/275 , H04L47/783 , H04L41/0896 , H04L47/30 , H04L41/0806 , H04J3/16 , H04J3/08 , H04B10/2575 , H04L12/437 , H04L49/102 , H04J3/14 , H04L47/10
CPC classification number: H04L47/783 , H04B10/25755 , H04B10/275 , H04J3/085 , H04J3/167 , H04L12/437 , H04L41/0806 , H04L41/0896 , H04L47/30 , H04L49/102 , H04J3/14 , H04L47/13
Abstract: A ring interconnect system comprises a plurality of nodes. Each node is connected to two other nodes to form a ring interconnect. Every pair of nodes is connected by an inter-node path for that pair of nodes distinct from the ring interconnect. Each of the nodes comprises a message buffer to buffer messages received from at least one device associated with the node. Each of the nodes also comprises activity level circuitry to transmit an activity indication, when a number of the messages in the message buffer is equal to or above a threshold, to each other node of the plurality of nodes via the respective inter-node paths. Each of the nodes also comprises arbitrator circuitry to receive the activity indications from each other node and from the activity level circuitry, and to allow ingress of a message from the message buffer onto the ring interconnect in dependence on the activity indications. Also provided is a method of operating a node of a ring interconnect system.
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公开(公告)号：US11016902B2
公开(公告)日：2021-05-25
申请号：US16382394
申请日：2019-04-12
Applicant: Arm Limited
Inventor： Geoffray Matthieu Lacourba , Andrew John Turner , Alex James Waugh
IPC: G06F12/0868 , G06F13/14 , G06F13/38
Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.
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公开(公告)号：US20150261700A1
公开(公告)日：2015-09-17
申请号：US14206236
申请日：2014-03-12
Applicant: ARM Limited
IPC: G06F13/26
CPC classification number: G06F13/26
Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.
Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。
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公开(公告)号：US20250103129A1
公开(公告)日：2025-03-27
申请号：US18474400
申请日：2023-09-26
Applicant: Arm Limited
Inventor： Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan , Munish Kumar , Vivek Asthana , Andrew John Turner , Alex James Waugh
IPC: G06F1/3296 , G06F12/0815
Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.
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公开(公告)号：US11784941B2
公开(公告)日：2023-10-10
申请号：US17374142
申请日：2021-07-13
Applicant: Arm Limited
Inventor： Alex James Waugh , Andrew John Turner , Shobhit Singhal
IPC: H04L47/762 , H04L47/78 , H04L12/42 , H04L47/122
CPC classification number: H04L47/762 , H04L12/42 , H04L47/122 , H04L47/781 , H04L2012/421
Abstract: An apparatus and method for operating a ring interconnect are disclosed. The ring interconnect has a plurality of nodes that are used to connect to associated components, and is arranged to transport a plurality of slots around the ring interconnect between the nodes in order to transfer items of traffic allocated into those slots between components connected to the nodes. For each item of traffic, one of the components acts as a source to allocate that item of traffic into a slot, and another components acts as destination to seek to remove that item of traffic from the slot. In a default mode of operation, the ring interconnect is arranged to allow all of the slots to be available for transfer of any items of traffic. Special slot management circuitry is provided that is responsive to a throughput alert trigger indicating a potential for occurrence of a throughput inhibiting condition, to cause a slot amongst the plurality of slots to be reserved as a special slot that is constrained for use only when one or more determined conditions are met. Further, the one or more determined conditions are arranged to cause the special slot to be used in a manner that seeks to avoid the throughput inhibiting condition arising.
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