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    Apparatus and method
    1.
    发明授权
    Apparatus and method 有权

    公开(公告)号：US11989134B2

    公开(公告)日：2024-05-21

    申请号：US17907178

    申请日：2021-03-08

    Applicant: ARM LIMITED

    Inventor： Yuval Elad ,  Jason Parker ,  Richard Roy Grisenthwaite ,  Simon John Craske ,  Alexander Donald Charles Chadwick

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10

    CPC classification number: G06F12/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

    Abstract: An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

    Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry
    2.
    发明授权
    Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry 有权

    公开(公告)号：US11263014B2

    公开(公告)日：2022-03-01

    申请号：US16531295

    申请日：2019-08-05

    Applicant: Arm Limited

    Inventor： Frederic Claude Marie Piry ,  Thomas Christoper Grocutt ,  Simon John Craske ,  Carlo Dario Fanara ,  Jean Sébastien Leroy

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Data processing apparatuses, methods of data processing, and non-transitory computer-readable media on which computer-readable code is stored defining logical configurations of processing devices are disclosed. In an apparatus, fetch circuitry retrieves a sequence of instructions and execution circuitry performs data processing operations with respect to data values in a set of registers. An auxiliary execution circuitry interface and a coprocessor interface to provide a connection to a coprocessor outside the apparatus are provided. Decoding circuitry generates control signals in dependence on the instructions of the sequence of instructions, wherein the decoding circuitry is responsive to instructions in a first subset of an instruction encoding space to generate the control signals to control the execution circuitry to perform the first data processing operations, and the decoding circuitry is responsive to instructions in a second subset of the instruction encoding space to generate the control signals in dependence on a configuration condition: to generate the control signals for the auxiliary execution circuitry interface when the configuration condition has a first state; and to generate the control signals for the coprocessor interface when the configuration condition has a second state.

    Selectively suppressing time intensive instructions based on a control value
    3.
    发明授权
    Selectively suppressing time intensive instructions based on a control value 有权

    公开(公告)号：US10963250B2

    公开(公告)日：2021-03-30

    申请号：US14911376

    申请日：2014-07-07

    Applicant: ARM LIMITED

    Inventor： Simon John Craske ,  Antony John Penton

    IPC: G06F9/30 ,  G06F9/48

    Abstract: The execution of time intensive instructions can lead to critical events being responded to late or not being responded to at all. An information processing apparatus comprises processing circuitry (60) for executing instructions comprising one or more time intensive instructions and exception generating circuitry (100) for generating at least one exception for the processing circuitry. The processing circuitry maintains a control value (20) for indicating whether or not the time intensive instructions can be executed. When a time intensive instruction is encountered, if the control value indicates that time intensive instructions cannot be executed then a first exception triggers the processing circuitry to suppress execution of the time intensive instruction. Alternatively, if the control value indicates that time intensive instructions can be executed, then the time intensive instruction is executed.

    Debugging in a data processing apparatus
    7.
    发明授权
    Debugging in a data processing apparatus 有权

    公开(公告)号：US09652348B2

    公开(公告)日：2017-05-16

    申请号：US14824299

    申请日：2015-08-12

    Applicant: ARM LIMITED

    Inventor： Michael John Williams ,  Simon John Craske

    IPC: G06F11/00 ,  G06F11/26 ,  G06F11/36 ,  G06F9/30 ,  G06F11/22

    CPC classification number: G06F11/26 ,  G06F9/30189 ,  G06F11/2236 ,  G06F11/3648

    Abstract: A data processing apparatus has a debug state in which processing circuitry 105 executes instructions received from the debug interface 115. Control changing circuitry 135 prohibits the execution of instructions in a predefined privilege mode when in the debug state if a control parameter has a predefined value. In response to a first exception being signalled while in the debug state, where the first exception is intended to be handled at the predefined privilege mode, and further in response to the control parameter having the predefined value, signalling circuitry 115 signals a second exception to be handled at a different privilege mode from the predefined privilege mode and sets information identifying a type of the first exception. Consequently, without having to enter the prohibited (predefined) privilege mode, the debugger 110 can be made aware of the first exception that would ordinarily be handled at the predefined, i.e. prohibited privilege mode.

    Apparatus and method for tracing exceptions
    8.
    发明授权
    Apparatus and method for tracing exceptions 有权

    公开(公告)号：US09606850B2

    公开(公告)日：2017-03-28

    申请号：US13795611

    申请日：2013-03-12

    Applicant: ARM LIMITED

    Inventor： John Michael Horley ,  Simon John Craske

    IPC: G06F15/00 ,  G06F9/44 ,  G06F11/07

    CPC classification number: G06F11/0766 ,  G06F11/0721

    Abstract: A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating circuitry that generates trace data packets in dependence on activity of the processing circuitry. The trace generating circuitry detects pending exceptions and, if an exception is detected to be pending, includes an indication of the pending exception in at least one trace data packet. By tracking when a particular exception is pended, rather than when it is selected for handling by the processing circuitry, it is possible to more precisely determine when the exception occurred, as opposed to when it is finally handled.

    Security domain prediction
    9.
    发明授权
    Security domain prediction 有权
    安全域预测

    公开(公告)号：US09501667B2

    公开(公告)日：2016-11-22

    申请号：US14310332

    申请日：2014-06-20

    Applicant: ARM Limited

    Inventor： Simon John Craske ,  Thomas Christopher Grocutt

    IPC: G06F9/38 ,  G06F7/04 ,  G06F17/30 ,  H04N7/16 ,  G06F21/79 ,  G06F21/55

    CPC classification number: G06F21/79 ,  G06F9/3806 ,  G06F21/554 ,  G06F2221/2141 ,  G06F2221/2149

    Abstract: A data processing apparatus supports operation in both a secure domain and a less secure domain. The secure domain has access to data that is not accessible when operating the less secure domain. Prediction circuitry generates a domain prediction indicating whether a given processing action (such as a memory access) is to be performed in association with the secure domain or with the less secure domain. In this way, an appropriate set of memory permission data for controlling access by different privilege levels in the domains may be selected and applied by an appropriate memory protection unit. If the domain prediction is incorrect, then the processing is stalled and the given processing action retried.

    Abstract translation: 数据处理装置支持安全域和较不安全域中的操作。 安全域可以访问在操作较不安全的域时无法访问的数据。 预测电路产生一个域预测，指示一个给定的处理动作（例如存储器访问）是否与安全域相关联地执行，或者与较不安全的域相关联地执行。 以这种方式，可以由适当的存储器保护单元选择适当的用于控制域中不同特权级别的访问的存储器许可数据集合。 如果域预测不正确，则停止处理并重试给定的处理动作。

    INTERRUPT SIGNAL ARBITRATION
    10.
    发明申请
    INTERRUPT SIGNAL ARBITRATION 有权
    中断信号仲裁

    公开(公告)号：US20150261700A1

    公开(公告)日：2015-09-17

    申请号：US14206236

    申请日：2014-03-12

    Applicant: ARM Limited

    Inventor： Simon John Craske ,  Michael Alexander Kennedy ,  Andrew John Turner ,  Richard Anthony Lane

    IPC: G06F13/26

    CPC classification number: G06F13/26

    Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.

    Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。

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