公开(公告)号：US20150261700A1

公开(公告)日：2015-09-17

申请号：US14206236

申请日：2014-03-12

Applicant: ARM Limited

Inventor： Simon John Craske ,  Michael Alexander Kennedy ,  Andrew John Turner ,  Richard Anthony Lane

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.

Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。

公开(公告)号：US10102160B2

公开(公告)日：2018-10-16

申请号：US14581290

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Michael Kennedy ,  Simon John Craske ,  Andrew Turner ,  Richard Anthony Lane

IPC: G06F13/32 ,  G06F13/16

Abstract: A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.

公开(公告)号：US20250086128A1

公开(公告)日：2025-03-13

申请号：US18820657

申请日：2024-08-30

Applicant: Arm Limited

Inventor： Timothy Nicholas Hay ,  Endre Papp ,  Richard Anthony Lane ,  Pedro Ochsendorf Portugal

IPC: G06F13/24

Abstract: An apparatus comprises a plurality of interfaces, each couplable to a respective one of a plurality of processing circuitries either in a higher criticality compliance state or a lower criticality compliance state. Each interface can receive from its respective processing circuitry interrupt signals destined to a target processing circuitry of the plurality of processing circuitries and transmit to its respective processing circuitry interrupt signals issued by a source processing circuitry of the plurality of processing circuitries. Control circuitry monitors the flow of the interrupt signals and determines whether the flow of interrupt signals exhibits a discrepancy with respect to an expected flow of interrupt signals, and performs a mitigation action in respect of said discrepancy to avoid violation of the higher criticality compliance state.

公开(公告)号：US09430421B2

公开(公告)日：2016-08-30

申请号：US14206236

申请日：2014-03-12

Applicant: ARM Limited

Inventor： Simon John Craske ,  Michael Alexander Kennedy ,  Andrew John Turner ,  Richard Anthony Lane

IPC: G06F13/26 ,  G06F13/38

CPC classification number: G06F13/26

Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.

Abstract translation: 中断控制器包括包括多个级的优先级仲裁器（8）。 这些级包括至少一个级，包括由多路复用器（14）形成的多个中断选择器，用于根据选择数据在一对潜在同时断言的中断信号之间进行选择。 优先级比较器（12）使用与各个中断信号相关联的优先级数据预先确定选择数据。