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Patent Agency Ranking
公开(公告)号：US20230063727A1
公开(公告)日：2023-03-02
申请号：US17462524
申请日：2021-08-31
Applicant: Arm Limited
Inventor： Anil Kumar Baratam , Yves Thomas Laplanche
IPC: H03K19/007 , H03K19/173 , H03K19/096
Abstract: Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.
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公开(公告)号：US11586445B2
公开(公告)日：2023-02-21
申请号：US16698862
申请日：2019-11-27
Applicant: Arm Limited
Inventor： Shardendu Shekhar , Andy Wangkun Chen , Anil Kumar Baratam , James Dennis Dodrill , Yew Keong Chong
Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.
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公开(公告)号：US11245388B2
公开(公告)日：2022-02-08
申请号：US16740138
申请日：2020-01-10
Applicant: Arm Limited
IPC: H03K19/0175 , H03K3/356 , H03K19/0185
Abstract: Various implementations described herein may refer to level shifter circuitry using current mirrors. For instance, in one implementation, a level shifter circuit may include a latch circuit configured to receive an input signal, where the latch circuit includes a plurality of transistors configured to generate an output signal based on the input signal. The level shifter circuit may also include a first current mirror circuit coupled to the latch circuit. The level shifter circuit may further include a second current mirror circuit coupled to the latch circuit, where the first current mirror circuit and the second current mirror circuit are configured to drive the output signal from a transient state voltage level to a steady state voltage level.
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公开(公告)号：US20210157603A1
公开(公告)日：2021-05-27
申请号：US16698862
申请日：2019-11-27
Applicant: Arm Limited
Inventor： Shardendu Shekhar , Andy Wangkun Chen , Anil Kumar Baratam , James Dennis Dodrill , Yew Keong Chong
Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.
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公开(公告)号：US10187063B1
公开(公告)日：2019-01-22
申请号：US15826647
申请日：2017-11-29
Applicant: Arm Limited
IPC: H03K3/356 , H03K19/173 , H03K3/012
Abstract: Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.
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