公开(公告)号：US10187063B1

公开(公告)日：2019-01-22

申请号：US15826647

申请日：2017-11-29

Applicant: Arm Limited

Inventor： Amanda Ashley Scantlin ,  Anil Kumar Baratam ,  James Dennis Dodrill ,  Susan Marie Graham

IPC: H03K3/356 ,  H03K19/173 ,  H03K3/012

Abstract: Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.