公开(公告)号：US11456727B2

公开(公告)日：2022-09-27

申请号：US17075614

申请日：2020-10-20

Applicant: Arm Limited

Inventor： Anil Kumar Baratam

IPC: H03K3/037 ,  H03K3/012

Abstract: Various implementations described herein are directed to a device having multiple stages. The device may have a first stage that provides a data path for an input data signal. The first stage may receive the input data signal, receive feedback signals, and provide an intermediate data signal based on the input data signal and/or the feedback signals. The device may have a second stage that provides set/reset signals based on the intermediate data signal and/or a clock signal. The second stage may receive the intermediate data signal, receive the clock signal, and generate the set/reset signals based on the intermediate data signal and the clock signal. The second stage may also provide the set/reset signals as the feedback signals to the first stage.

公开(公告)号：US20220123737A1

公开(公告)日：2022-04-21

申请号：US17075614

申请日：2020-10-20

Applicant: Arm Limited

Inventor： Anil Kumar Baratam

IPC: H03K3/037 ,  H03K3/012

Abstract: Various implementations described herein are directed to a device having multiple stages. The device may have a first stage that provides a data path for an input data signal. The first stage may receive the input data signal, receive feedback signals, and provide an intermediate data signal based on the input data signal and/or the feedback signals. The device may have a second stage that provides set/reset signals based on the intermediate data signal and/or a clock signal. The second stage may receive the intermediate data signal, receive the clock signal, and generate the set/reset signals based on the intermediate data signal and the clock signal. The second stage may also provide the set/reset signals as the feedback signals to the first stage.

公开(公告)号：US20210305985A1

公开(公告)日：2021-09-30

申请号：US16991018

申请日：2020-08-12

Applicant: Arm Limited

Inventor： Anil Kumar Baratam

IPC: H03K19/094 ,  H03K19/0944 ,  H03K19/17736 ,  H03K19/173 ,  H03K3/0233

Abstract: Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.

公开(公告)号：US09306545B2

公开(公告)日：2016-04-05

申请号：US14154757

申请日：2014-01-14

Applicant: ARM LIMITED

Inventor： Anil Kumar Baratam

IPC: H03K3/289 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop.

Abstract translation: 具有主锁存器和从锁存器的主从触发器电路具有基于时钟信号和门控控制信号产生门控时钟信号的时钟发生电路。 当选通控制信号具有第一值时，门控时钟信号具有取决于时钟信号的值，而当门控控制信号具有第二值时，门控时钟信号具有与时钟信号无关的固定值。 主从触发器电路的至少一个组件由门控时钟信号控制，从而可以降低动态开关功率。 门控控制信号取决于输入信号或主锁存器内的信号，与从锁存器中的从属信号和触发器的输出信号无关。

公开(公告)号：US12068745B2

公开(公告)日：2024-08-20

申请号：US17462524

申请日：2021-08-31

Applicant: Arm Limited

Inventor： Anil Kumar Baratam ,  Yves Thomas Laplanche

IPC: H03K19/007 ,  H03K19/096 ,  H03K19/173

CPC classification number: H03K19/0075 ,  H03K19/096 ,  H03K19/1737

Abstract: Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

公开(公告)号：US20240249790A1

公开(公告)日：2024-07-25

申请号：US18100614

申请日：2023-01-24

Applicant: Arm Limited

Inventor： Yannis Jallamion-Grive ,  Yunpeng Cai ,  Mohammed Adnan Addou ,  Anil Kumar Baratam ,  Denil Das Kolady ,  Chandru Tavarekere Krishnegowda ,  Jad Mohdad ,  Yves Thomas Laplanche ,  Yannick Marc Nevers

IPC: G11C29/30 ,  G11C29/12

CPC classification number: G11C29/30 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2029/3202

Abstract: Various implementations described herein are related to a device having a memory architecture with a register bank and multiple latches. The multiple latches may have first latches that receive multi-bit data as input and provide the multi-bit data as output, and multiple latches may have second latches coupled to the first latches so as to receive the multi-bit data from the first latches and then store the multi-bit data.

公开(公告)号：US10355674B2

公开(公告)日：2019-07-16

申请号：US15658214

申请日：2017-07-24

Applicant: ARM Limited

Inventor： Anil Kumar Baratam ,  Nruthya Nagesh Prabhu ,  Yves Thomas Laplanche

IPC: H03K3/356 ,  H03K17/687

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

公开(公告)号：US20210218389A1

公开(公告)日：2021-07-15

申请号：US16740138

申请日：2020-01-10

Applicant: Arm Limited

Inventor： Navaneeth Narayanan Namboodiri Rajalakshmi ,  Anil Kumar Baratam

IPC: H03K3/356 ,  H03K19/0185

Abstract: Various implementations described herein may refer to level shifter circuitry using current mirrors. For instance, in one implementation, a level shifter circuit may include a latch circuit configured to receive an input signal, where the latch circuit includes a plurality of transistors configured to generate an output signal based on the input signal. The level shifter circuit may also include a first current mirror circuit coupled to the latch circuit. The level shifter circuit may further include a second current mirror circuit coupled to the latch circuit, where the first current mirror circuit and the second current mirror circuit are configured to drive the output signal from a transient state voltage level to a steady state voltage level.

公开(公告)号：US10922465B2

公开(公告)日：2021-02-16

申请号：US16144688

申请日：2018-09-27

Applicant: Arm Limited

Inventor： Anil Kumar Baratam ,  Subramanya Ravindra Shindagikar

IPC: G06F30/39 ,  G11C7/10 ,  H03K19/21 ,  G11C11/40

Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

公开(公告)号：US20190028091A1

公开(公告)日：2019-01-24

申请号：US15658214

申请日：2017-07-24

Applicant: ARM Limited

Inventor： Anil Kumar Baratam ,  Nruthya Nagesh Prabhu ,  Yves Thomas Laplanche

IPC: H03K3/356 ,  H03K17/687

CPC classification number: H03K3/356121 ,  H03K3/012 ,  H03K17/6872

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.