公开(公告)号：US20240169465A1

公开(公告)日：2024-05-23

申请号：US18499045

申请日：2023-10-31

Applicant: Arm Limited

Inventor： Naveen Kumar Singh ,  Frank Klaeboe Langtind

IPC: G06T1/20 ,  G06T1/60 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40

Abstract: When generating a graphics processing output by assembling a sequence of one or more of primitives to be processed, vertex attribute processing is performed for vertices of assembled primitives to generate one or more processed vertex attributes for vertices of the assembled primitives. Processed vertex attributes for vertices of assembled primitives are stored in a first storage, and additionally in a second storage. Then when obtaining processed vertex attributes for an assembled primitive, it is checked whether processed vertex attributes for the vertices of the primitive are present in the second storage, and when they are, the processed vertex attributes are read from the second storage, but when the processed vertex attributes are not in the second storage, they are read from the first storage instead.

公开(公告)号：US11790479B2

公开(公告)日：2023-10-17

申请号：US17163289

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Frank Klaeboe Langtind ,  Andreas Due Engh-Halstvedt

IPC: G06T1/20 ,  G06T1/60 ,  G06T11/20

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/203

Abstract: When generating a graphics processing output, a sequence of one or more of primitives to be processed when generating the output is assembled from a set of vertex indices provided for the output based on primitive configuration information provided for the output, each assembled primitive of the sequence of assembled primitives comprising an identifier for the primitive and a set of one or more vertex indices for the primitive. One or more attributes for vertices of the assembled primitives are then shaded and fetched based on the vertex indices of the assembled primitives. The assembled primitives including their shaded fetched vertex attribute(s) are then provided to later stages of the graphics processing pipeline for processing.

公开(公告)号：US11189005B1

公开(公告)日：2021-11-30

申请号：US17004797

申请日：2020-08-27

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Jorn Nystad ,  Olof Henrik Uhrenholt ,  Frank Klaeboe Langtind

IPC: G06T1/20 ,  G06T1/60 ,  G06T17/10 ,  G06T9/00 ,  G06T15/00

Abstract: A method of operating a graphics processor that is configured to execute a graphics processing pipeline is provided. The method comprises the graphics processor reading, from an index buffer in external memory, a block of data comprising plural sets of indices, each set of indices comprising a sequence of indices indexing a set of vertices that defines a primitive of a plurality of primitives to be processed by the graphics processing pipeline. The graphics processor compresses the block of data to form a compressed version of the block of data, and stores the compressed version of the block of data in an internal memory of the graphics processor.

公开(公告)号：US12243149B2

公开(公告)日：2025-03-04

申请号：US18184094

申请日：2023-03-15

Applicant: Arm Limited

Inventor： Wei Shao ,  Frank Klaeboe Langtind

IPC: G06T15/00 ,  G06T11/40 ,  G06T15/80

Abstract: When performing tile-based graphics processing, a first vertex shading operation to generate vertex shaded position data for vertices is performed, and the vertex shaded position data used to prepare primitive lists indicating which primitives should be rendered for respective rendering tiles. Then, when processing a tile, a second vertex shading operation is performed for vertices of primitives for the tile for which fragments have been generated by a rasteriser prior to rendering the graphics fragments, to generate vertex shaded non-position attribute data for the vertices, based on the results of early depth testing before the fragments are rendered.

公开(公告)号：US20240169643A1

公开(公告)日：2024-05-23

申请号：US18509285

申请日：2023-11-14

Applicant: Arm Limited

Inventor： Rafal Stepuch ,  Frank Klaeboe Langtind ,  Andreas Due Engh-Halstvedt

IPC: G06T15/00 ,  G06F9/50

CPC classification number: G06T15/005 ,  G06F9/50

Abstract: When processing primitives in a tile-based graphics processing system in which a render output is sub-divided into a plurality of tiles for rendering, before a primitive is written to a primitive list corresponding to a region of the render output, it is first written to one or more primitive queues allocated to respective regions of the render output. To write the primitives to primitive lists, primitives are written together from a primitive queue allocated to a region of the render output to the primitive list for that region of the render output, in a single primitive list write cycle.

公开(公告)号：US20230132068A1

公开(公告)日：2023-04-27

申请号：US17511261

申请日：2021-10-26

Applicant: Arm Limited

Inventor： Michael Martin Klock ,  Philip Carlos Garcia ,  Frank Klaeboe Langtind ,  Peter Anthony Hearne

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: Disclosed subject matter relates generally to graphics processing, and relates more particularly to processing graphics vertex content.

公开(公告)号：US11189073B2

公开(公告)日：2021-11-30

申请号：US16825346

申请日：2020-03-20

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind ,  Mark Underwood

IPC: G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06T1/20

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.

公开(公告)号：US20210295584A1

公开(公告)日：2021-09-23

申请号：US16825346

申请日：2020-03-20

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind ,  Mark Underwood

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/80

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.

公开(公告)号：US20250131523A1

公开(公告)日：2025-04-24

申请号：US18918880

申请日：2024-10-17

Applicant: Arm Limited

Inventor： Frank Klaeboe Langtind ,  Olof Henrik Uhrenholt

IPC: G06T1/20

Abstract: A tile-based graphics processor performs first and second processing passes to generate a render output. The first processing pass generates data that is used in the second processing pass to determine which primitives to process for which rendering tiles. The first processing pass is performed by a geometry processing control unit assembling primitives, and one or more programmable processing units transforming geometry data defining the primitives, and processing the transformed geometry data to generate the data.

公开(公告)号：US20250111576A1

公开(公告)日：2025-04-03

申请号：US18478666

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Rafal Stepuch ,  Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind

IPC: G06T15/00 ,  G06T15/04

Abstract: When preparing and storing primitive lists in a tile-based graphics processing system, one or more primitive list pointer arrays store pointers, each pointer indicating a location in storage of one or more of the primitive lists. A further pointer array stores further pointers, each further pointer indicating a location in storage of one or more of the primitive list pointer arrays.