公开(公告)号：US20250111462A1

公开(公告)日：2025-04-03

申请号：US18478078

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Philip Carlos Garcia ,  Mark Underwood

IPC: G06T1/20

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced. In particular, there is disclosed a mechanism for suspending the sequence of rendering jobs (so that it may subsequently be resumed).

公开(公告)号：US20250110747A1

公开(公告)日：2025-04-03

申请号：US18478345

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Maochang Dang ,  Andreas Danner Nilsen ,  Mark Underwood ,  Brian Gordon Pearson ,  Espen Amodt ,  Xinyu Chen

IPC: G06F9/38 ,  G06F9/30

Abstract: A method of preparing a command stream for a parallel processor, comprising: analysing the command stream to detect at least a first dependency; generating at least one timeline dependency point responsive to detecting the first dependency; determining a latest action for the first dependency to derive a completion stream timeline point for the first dependency; comparing the completion stream timeline point for the first dependency with a completion stream timeline point for a second dependency to determine a latest stream timeline point; generating at least one command stream synchronization control instruction according to the latest stream timeline point; and providing the command stream and the at least one command stream synchronization control instruction to an execution unit of the parallel processor.

公开(公告)号：US10824467B2

公开(公告)日：2020-11-03

申请号：US16056927

申请日：2018-08-07

Applicant: Arm Limited

Inventor： Mark Underwood ,  Hakan Lars-Goran Persson

IPC: G06F9/455 ,  G06F9/48

Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by the accelerator. When a request for processing includes protected content, the host processor includes within a command for a command stream, an indication that a subsequent sequence of one or more command(s) within that command stream associated with the protected content is to be implemented by the accelerator in a protected mode of operation. Then, when that command is executed, the accelerator initiates or requests a switch into the protected mode of operation.

公开(公告)号：US10732978B2

公开(公告)日：2020-08-04

申请号：US16112094

申请日：2018-08-24

Applicant: Arm Limited

Inventor： Mark Underwood ,  Hakan Lars-Goran Persson

IPC: G06F9/38 ,  G06F9/52 ,  G06F9/30

Abstract: A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by a command stream execution unit of the accelerator. A pre-execution unit is provided that is operable to interpret commands fetched from command stream storage before the command is provided to the command stream execution unit for implementation to determine whether the pre-execution unit is able to perform an action in response to the command and, when the pre-execution unit is able to do so, to perform an action in response to the command.

公开(公告)号：US20200065095A1

公开(公告)日：2020-02-27

申请号：US16107250

申请日：2018-08-21

Applicant: Arm Limited

Inventor： Mark Underwood ,  Hakan Lars-Goran Persson ,  Arne Aas

IPC: G06F9/30 ,  G06F9/38

Abstract: When executing a program on a data processor comprising an execution unit for executing instructions in a program to be executed by the data processor, the execution unit being associated with one or more hardware units operable to execute instructions, at least one instruction in a program is associated with an indication of whether the instruction should be issued directly for execution by a hardware unit or should be intercepted during its execution by the execution unit. The execution unit then, when decoding the instruction for execution by a hardware unit in the program, determines from the indication associated with the instruction whether the instruction should be issued directly for execution by a hardware unit or intercepted during its execution by the execution unit, and issues the instruction for execution by a hardware unit directly, or pauses execution of the instruction and performs another operation, accordingly.

公开(公告)号：US10824468B2

公开(公告)日：2020-11-03

申请号：US16273448

申请日：2019-02-12

Applicant: Arm Limited

Inventor： Mark Underwood ,  Sandeep Kakarlapudi ,  Robert John Rees

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/0837 ,  G06F9/38 ,  G06F9/52

Abstract: A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.

公开(公告)号：US20250111467A1

公开(公告)日：2025-04-03

申请号：US18894496

申请日：2024-09-24

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Mark Underwood ,  Daren Croxford ,  Joseph Michael Richardson

IPC: G06T1/20 ,  G06T1/60

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks for different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks are enforced.

公开(公告)号：US20250111464A1

公开(公告)日：2025-04-03

申请号：US18478131

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Mark Underwood ,  Wing-Tsi Henry Wong ,  Olof Henrik Uhrenholt ,  Philip Carlos Garcia ,  Daren Croxford

IPC: G06T1/20

Abstract: When performing a sequence of rendering jobs, rendering tasks for separate rendering jobs are permitted to overlap within the graphics processor's processing (shader) cores. A record is maintained of which rendering tasks are currently being processed by the graphics processor's processing (shader) cores which record can then be used to enforce any data (processing) dependencies between different rendering jobs.

公开(公告)号：US20220382587A1

公开(公告)日：2022-12-01

申请号：US17705856

申请日：2022-03-28

Applicant: Arm Limited

Inventor： Andreas Danner Nilsen ,  Mark Underwood ,  Arne Aas ,  Andreas Due Engh-Halstvedt ,  Shan Wu

IPC: G06F9/50 ,  G06F9/38

Abstract: A data processing system is disclosed that includes one or more processors that can perform producer processes to produce work and consumer processes that can consume work produced by a producer process. The system includes a pool of plural communication resources that may be used for communications between a producer process and a consumer process. The system tracks the usage of communication resources of the pool of communication resources, and allocates a communication resource from the pool of communication resources based on the tracking.

公开(公告)号：US11189073B2

公开(公告)日：2021-11-30

申请号：US16825346

申请日：2020-03-20

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind ,  Mark Underwood

IPC: G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06T1/20

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.