Logical Interleaver
    11.
    发明申请
    Logical Interleaver 审中-公开

    公开(公告)号:US20170338836A1

    公开(公告)日:2017-11-23

    申请号:US15157814

    申请日:2016-05-18

    Applicant: ARM Limited

    CPC classification number: H03M13/2906 H03M13/05 H03M13/27 H03M13/2792

    Abstract: Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device may include a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit may interleave data bits from multiple different data words and store modified data words based on the multiple different data words.

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