公开(公告)号：US20210326268A1

公开(公告)日：2021-10-21

申请号：US17269388

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Ruben Borisovich AYRAPETYAN ,  Graeme Peter BARNES ,  Richard Roy GRISENTHWAITE

IPC: G06F12/1027 ,  G06F12/14

Abstract: An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks. This provides a very flexible and efficient mechanism for performing tag-guarded memory access operations.

公开(公告)号：US20190095389A1

公开(公告)日：2019-03-28

申请号：US16094224

申请日：2017-03-29

Applicant: ARM LIMITED

Inventor： Graeme Peter BARNES ,  Stuart David BILES

IPC: G06F16/23 ,  G06F16/245 ,  G06F16/22 ,  G06F9/30 ,  G06F13/28

Abstract: An apparatus is provided comprising storage elements to store data blocks, where each data block has capability metadata associated therewith identifying whether the data block specifies a capability, at least one capability type being a bounded pointer. Processing circuitry is then arranged to be responsive to a bulk capability metadata operation identifying a plurality of the storage elements, to perform an operation on the capability metadata associated with each data block stored in the plurality of storage elements. Via a single specified operation, this hence enables query and/or modification operations to be performed on multiple items of capability metadata, hence providing more efficient access to such capability metadata.

公开(公告)号：US20180364980A1

公开(公告)日：2018-12-20

申请号：US15626454

申请日：2017-06-19

Applicant: ARM Limited

Inventor： Daniel ARULRAJ ,  Graeme Peter BARNES ,  Lee EISEN ,  Gary GORMAN

IPC: G06F7/50 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F7/50 ,  G06F3/0622 ,  G06F3/0638 ,  G06F3/0673 ,  G06F7/02 ,  G06F12/1416 ,  G06F2212/1052 ,  H03M7/24 ,  H03M7/30 ,  H03M7/3066 ,  H03M7/3091 ,  H03M7/702

Abstract: A data processing apparatus is provided, for performing a determination of whether a value falls within a boundary defined by a lower limit between 0 and 2m and an upper limit between 0 and 2m. The apparatus includes storage circuitry that stores each of the lower limit and the upper limit in a compressed form as a mantissa of q

公开(公告)号：US20200225872A1

公开(公告)日：2020-07-16

申请号：US16647742

申请日：2019-01-23

Applicant: Arm Limited

Inventor： Graeme Peter BARNES

IPC: G06F3/06

Abstract: An apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address. The memory access circuitry is responsive to a sequence of received target addresses specifying a sequence of addressed locations to perform a non-tag-guarded memory access that does not perform the guard-tag check to a subset of the sequence of addressed locations.

公开(公告)号：US20200050454A1

公开(公告)日：2020-02-13

申请号：US16607462

申请日：2018-04-27

Applicant: ARM LIMITED

Inventor： Graeme Peter BARNES

IPC: G06F9/30 ,  G06F9/32

Abstract: An apparatus and method are provided for managing a capability domain. The apparatus has processing circuitry for executing instructions, the processing circuitry when in a default state being arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry when executing the instructions. A program counter capability storage element is also provided to store a program counter capability used by the processing circuitry to determine a program counter value. The program counter capability is arranged to identify a capability state for the processing circuitry. The processing circuitry is then arranged, when the capability state indicates the default state, to operate in the capability domain. However, when the capability state indicates the executive state, the processing circuitry is arranged to operate in a manner less constrained than when in the default state so as to allow modification of the capability domain. This provides a simple and effective mechanism for selectively allowing the apparatus to modify the capability domain.

公开(公告)号：US20200042464A1

公开(公告)日：2020-02-06

申请号：US16055240

申请日：2018-08-06

Applicant: Arm Limited

Inventor： Daniel ARULRAJ ,  Lee Evan EISEN ,  Graeme Peter BARNES

IPC: G06F12/14 ,  G06F9/30

Abstract: An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p−q−e bits of the lower limit and the upper limit is derivable from the most significant p−q−e bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2x regions of size 2n1, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.

公开(公告)号：US20190258574A1

公开(公告)日：2019-08-22

申请号：US16334095

申请日：2017-08-18

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Graeme Peter BARNES

IPC: G06F12/0815 ,  G06F12/10

Abstract: A data processing apparatus 2 includes a cache memory 8 for storing data items to be accessed. Coherency control circuitry 20 controls coherency between data items stored within the cache memory and one or more other copies of the data items stored outside the cache memory. A data access buffer 6 buffers a plurality of data access to respective data items stored within the cache memory. Access control circuitry 20 is responsive to coherency statuses managed by the coherency control circuitry for the plurality of data items to be subject to data access operations to be performed together atomically as an atomic set of data accesses to ensure that the coherency statuses for all of these data items permit all of the atomic set of data accesses to be performed within the cache memory before the set of atomic data accesses are commenced.

公开(公告)号：US20190026236A1

公开(公告)日：2019-01-24

申请号：US16070801

申请日：2016-12-23

Applicant: ARM LIMITED

Inventor： Graeme Peter BARNES

IPC: G06F12/14 ,  G06F21/64 ,  G06F21/54 ,  G06F21/12 ,  G06F9/30

Abstract: An apparatus and method are provided for generating signed bounded pointers from general purpose specified data, for example data that may exist within a backing store such as a disk. The apparatus has processing circuitry that is responsive to a bounded pointer generation request to perform a generation operation to generate a bounded pointer from the specified data provided at least one generation condition is met. The bounded pointer comprises a pointer value and associated attributes, and the associated attributes include range information indicative of an allowable range of addresses when using the pointer value. The processing circuitry is further responsive to detection from the specified data that the bounded pointer to be generated is a signed bounded pointer incorporating a signature, to perform as part of the generation operation, at least in the presence of a signing condition being met, an insert signature operation during which the signature is determined from a portion of the specified data and incorporated within the generated bounded pointer. Thereafter, the generated bounded pointer is output for storage in a storage element of the apparatus.

公开(公告)号：US20180349294A1

公开(公告)日：2018-12-06

申请号：US15771107

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Graeme Peter BARNES

IPC: G06F12/14 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F9/46 ,  G06F9/54

CPC classification number: G06F12/1441 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/324 ,  G06F9/34 ,  G06F9/3861 ,  G06F9/468 ,  G06F9/542 ,  G06F2212/1052

Abstract: An apparatus and method are provided for managing bounded pointers. The apparatus has processing circuitry to execute a sequence of instructions, and a plurality of storage elements accessible to the processing circuitry, for storage of bounded pointers and non-bounded pointers. Each bounded pointer has explicit range information associated therewith indicative of an allowable range of memory addresses when using the bounded pointer. A current range check storage element is then used to store a current range check state for the processing circuitry. When the current range check state indicates a default state, the processing circuitry is responsive to execution of a memory access instruction identifying a pointer to be used to identify a memory address, to perform a range check operation to determine whether access to that memory address is permitted. In particular, when the memory access instruction identifies as the pointer one of the bounded pointers, the range check operation is performed with reference to the explicit range information associated with that bounded pointer. If instead the memory access instruction identifies a non-bounded pointer, the range check operation is performed with reference to default range information defined for the processing circuitry. On detection of at least one event, the current range check state is set to an executive state. When in the executive state, the processing circuitry is responsive to execution of a memory access instruction to disable the range check operation when the identified pointer is a non-bounded pointer. This provides an efficient, but controlled, mechanism for enabling the set of bounded pointers available to the processing circuitry to be altered.