公开(公告)号：US10591977B2

公开(公告)日：2020-03-17

申请号：US14965184

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Mark David Werkheiser ,  Dominic William Brown ,  Ashley John Crawford ,  Paul Gilbert Meyer

IPC: G06F1/32 ,  G06F1/3234 ,  G06F12/0813 ,  G06F12/0831

Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.

公开(公告)号：US10095631B2

公开(公告)日：2018-10-09

申请号：US14965214

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Paul Gilbert Meyer ,  Gurunath Ramagiri

IPC: G06F12/1018 ,  G06F3/06 ,  G06F13/40

Abstract: A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.