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公开(公告)号：US20210117192A1
公开(公告)日：2021-04-22
申请号：US16656385
申请日：2019-10-17
Applicant: Arm Limited
Inventor： John David Robson , Sean Tristram LeGuay Ellis , William Robert Stoye
IPC: G06F9/30
Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file.
Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.-
公开(公告)号：US20250014259A1
公开(公告)日：2025-01-09
申请号：US18763478
申请日：2024-07-03
Applicant: Arm Limited
Inventor： Yoav Asher Levy , Jakob Axel Fries , William Robert Stoye
Abstract: A graphics processor operable to render frames that represent a view of a scene using a ray tracing process includes a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process. The ray tracing circuit comprises a ray testing circuit operable to perform ray intersection tests for nodes of a ray tracing acceleration data structure and storage local to the ray testing circuit for storing data representative of one or more nodes of a ray tracing acceleration data structure for use by the ray testing circuit. Rays for testing by the ray testing circuit are selected from a pool of one or more rays to be tested based on an indication of the ray tracing acceleration data structure node or nodes that have been stored in the local storage of the ray testing circuit.
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公开(公告)号：US20240371076A1
公开(公告)日：2024-11-07
申请号：US18616496
申请日：2024-03-26
Applicant: Arm Limited
Inventor： Richard Edward Bruce , William Robert Stoye , Jakob Axel Fries
Abstract: A method of operating a graphics processor to perform ray tracing. The graphics processor includes a ray tracing circuit that can be messaged by the graphics processor's programmable execution unit during execution of a program to perform a respective traversal of the at least one ray tracing acceleration data structure to be traversed for that ray. The ray tracing circuit when returning rays' processing to the programmable execution unit is operable to group rays together for continued execution by the programmable execution unit as a respective thread group.
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公开(公告)号：US20240371075A1
公开(公告)日：2024-11-07
申请号：US18616469
申请日：2024-03-26
Applicant: Arm Limited
Inventor： Richard Edward Bruce , William Robert Stoye , Jakob Axel Fries , Wing-Tsi Henry Wong
IPC: G06T15/06
Abstract: A method of operating a graphics processor to perform ray tracing. The graphics processor includes a ray tracing circuit that can be messaged by the graphics processor's programmable execution unit during execution of a program to perform a respective traversal of the at least one ray tracing acceleration data structure to be traversed for that ray. The ray tracing circuit may need to stop a ray's traversal to return the ray's processing to the programmable execution unit before the ray's traversal is subsequently restarted. In that case, the ray's traversal is restarted from the beginning.
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Patent Agency Ranking
公开(公告)号：US12106422B2
公开(公告)日：2024-10-01
申请号：US17805453
申请日：2022-06-04
Applicant: Arm Limited
Inventor： Richard Bruce , William Robert Stoye , Mathieu Jean Joseph Robart
IPC: G06T15/06 , G06F16/901 , G06T15/00
CPC classification number: G06T15/06 , G06F16/9027 , G06T15/005 , G06T2210/21
Abstract: An instruction (or set of instructions) that can be included in a program to perform a ray tracing acceleration data structure traversal, with individual execution threads in a group of execution threads executing the program performing a traversal operation for a respective ray in a corresponding group of rays such that the group of rays performing the traversal operation together. The instruction(s), when executed by the execution threads in respect of a node of the ray tracing acceleration data structure, cause one or more rays from the group of plural rays that are performing the traversal operation together to be tested for intersection with the one or more volumes associated with the node being tested. A result of the ray-volume intersection testing can then be returned for the traversal operation.
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公开(公告)号：US12067668B2
公开(公告)日：2024-08-20
申请号：US17805387
申请日：2022-06-03
Applicant: Arm Limited
Inventor： Richard Bruce , William Robert Stoye , Mathieu Jean Joseph Robart , Jørn Nystad
CPC classification number: G06T15/06 , G06T15/005 , G06T2210/21
Abstract: There is provided an instruction, or instructions, that can be included in a program to perform a ray tracing operation, with individual execution threads in a group of execution threads executing the program performing the ray tracing operation for a respective ray in a corresponding group of rays such that the group of rays performing the ray tracing operation together. The instruction(s), when executed by the execution threads will cause one or more rays from the group of plural rays to be tested for intersection with a set of primitives. A result of the ray-primitive intersection testing can then be returned for the traversal operation.
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17.发明授权公开(公告)号：US11442731B2
公开(公告)日：2022-09-13
申请号：US16656385
申请日：2019-10-17
Applicant: Arm Limited
Inventor： John David Robson , Sean Tristram LeGuay Ellis , William Robert Stoye
IPC: G06F9/30
Abstract: A data processor includes an execution unit that executes instructions to perform data processing operations, a register file operable to store data values for use by and produced by the execution unit, and a buffer intermediate between the register file for providing data values from the register file to the execution unit for use when executing an instruction, and to receive output data values from the execution unit for writing to the register file.
Instructions to be executed by the execution unit of the data processor have associated buffer eviction priority indications representative of a priority for eviction from the buffer of an output data value that will be generated when executing the instruction. The buffer eviction priority indications are then used when selecting data values to evict from the buffer.-
公开(公告)号：US10891708B1
公开(公告)日：2021-01-12
申请号：US16695009
申请日：2019-11-25
Applicant: Arm Limited
Inventor： Sean Tristram LeGuay Ellis , William Robert Stoye
Abstract: A shader program to be executed by a graphics processor has associated with it a start instruction indication, indicating the instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread, and includes a set-entry instruction, which, when executed by a thread, will cause the start instruction indication to be modified to indicate a different instruction in the sequence of instructions for the program at which execution of the program should be started by an execution thread. When executing the program, execution threads determine from the start instruction indication associated with the program, the instruction in the sequence of instructions for the program at which they should start execution of the program.
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公开(公告)号：US10157132B1
公开(公告)日：2018-12-18
申请号：US15661200
申请日：2017-07-27
Applicant: ARM Limited
Inventor： Edvard Fielding , Andreas Due Engh-Halstvedt , Jorn Nystad , Antonio Garcia Guirado , William Robert Stoye , Ian Rudolf Bratt
IPC: G06F12/00 , G06F13/00 , G06F13/28 , G06F12/0811 , G06F12/0875 , G06F12/0862 , G06F12/0846 , G06F12/0868
Abstract: A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.
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