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公开(公告)号：US20240169464A1
公开(公告)日：2024-05-23
申请号：US18499029
申请日：2023-10-31
Applicant: Arm Limited
Inventor： Frank Klaeboe Langtind , Andreas Due Engh-Halstvedt
Abstract: When generating a graphics processing output by assembling a sequence of one or more of primitives to be processed from a set of vertex indices provided for the output based on primitive configuration information provided for the output, one or more vertex packets are generated using the vertex indices for the assembled primitives, each vertex packet comprising a plurality of vertices of the assembled primitives. After a threshold number of vertices have been allocated to a vertex packet, vertex attribute processing for the vertices of the vertex packet is triggered, to thereby generate a vertex packet comprising processed vertex attributes for the vertices of the vertex packet. The assembled primitives and the generated vertex packets are then provided to later stages of the graphics processing pipeline for processing.
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公开(公告)号：US11789867B2
公开(公告)日：2023-10-17
申请号：US16742495
申请日：2020-01-14
Applicant: Arm Limited
Inventor： Olof Henrik Uhrenholt , Andreas Due Engh-Halstvedt
IPC: G06F12/0811 , G06F9/30 , G06F9/38 , G06F3/06
CPC classification number: G06F12/0811 , G06F3/064 , G06F3/0623 , G06F3/0685 , G06F9/30196 , G06F9/3877
Abstract: A data processing system includes a cache system configured to transfer data stored in the memory system to a processor and to transfer data from the processor to the memory system. The cache system comprises a cache and a data encoder associated with the cache that is configured to encode uncompressed data from the cache for storing in the memory system in a compressed format, and decode compressed data from the memory system for storing in the cache in an uncompressed format.
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公开(公告)号：US11216993B2
公开(公告)日：2022-01-04
申请号：US16697903
申请日：2019-11-27
Applicant: Arm Limited
Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Primitive data for rendering the primitive is then stored either in a combined data structure in memory that is associated with a plurality of different regions of the render output, or is stored in a respective data structure for each region of the render output it is determined the primitive should be rendered for. Which manner the primitive data is stored is determined in dependence on a property, e.g. a coverage, of the primitive.
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公开(公告)号：US11049216B1
公开(公告)日：2021-06-29
申请号：US16748721
申请日：2020-01-21
Applicant: Arm Limited
Abstract: A graphics processor that rasterises input primitives to generate graphics fragments to be processed and renders the graphics fragments to generate a first, higher resolution version of a render output. When processing of a render output is stopped before the render output is finished, the first resolution version of the render output is downsampled to a second, lower resolution and the downsampled data elements at the second resolution are written out together with a set of difference values indicative of the differences between the data elements at the first resolution and the downsampled data elements at the second resolution. Then, when processing of the render output is resumed, these values can be loaded in and used to reconstruct the array of data elements at the first resolution for use when continuing processing of the render output.
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公开(公告)号：US10650580B2
公开(公告)日：2020-05-12
申请号：US16026402
申请日：2018-07-03
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Klaeboe Langtind
Abstract: A graphics processing pipeline includes: a position shader, a tiler, a pool of memory for storing primitive lists and vertex shaded attributes data for vertices, a varying-only vertex shader, and a fragment frontend and shader. The position shader performs vertex shading for the positional attributes of the vertices of a set of vertices to be processed by the graphics processing pipeline. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output. When the tiler determines that a vertex should be processed further to generate the render output, it allocates memory space in the memory pool for storing vertex shaded attributes data for the vertex. Vertex shaded attributes data for the vertex is then stored in the allocated space in the memory pool for later use, e.g., by the fragment frontend and shader.
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Patent Agency Ranking
公开(公告)号：US10331404B2
公开(公告)日：2019-06-25
申请号：US14584237
申请日：2014-12-29
Applicant: ARM Limited
Inventor： Jorn Nystad , Andreas Due Engh-Halstvedt , Simon Alex Charles
Abstract: Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantise and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.
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公开(公告)号：US20190012829A1
公开(公告)日：2019-01-10
申请号：US16026402
申请日：2018-07-03
Applicant: Arm Limited
Inventor： Andreas Due Engh-Halstvedt , Frank Klaeboe Langtind
Abstract: A graphics processing pipeline includes: a position shader, a tiler, a pool of memory for storing primitive lists and vertex shaded attributes data for vertices, a varying-only vertex shader, and a fragment frontend and shader. The position shader performs vertex shading for the positional attributes of the vertices of a set of vertices to be processed by the graphics processing pipeline. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output. When the tiler determines that a vertex should be processed further to generate the render output, it allocates memory space in the memory pool for storing vertex shaded attributes data for the vertex. Vertex shaded attributes data for the vertex is then stored in the allocated space in the memory pool for later use, e.g., by the fragment frontend and shader.
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公开(公告)号：US10089709B2
公开(公告)日：2018-10-02
申请号：US15208459
申请日：2016-07-12
Applicant: ARM Limited
Inventor： Andreas Due Engh-Halstvedt , David James Bermingham , Amir Kleen , Jørn Nystad , Kenneth Edvard Østby
Abstract: A graphics processing unit 3 includes a rasterizer 25, a thread spawner 40, a programmable execution unit 41, a varying interpolator 42, a texture mapper 43, and a blender 29. The programmable execution unit 41 is able to communicate with the varying interpolator 42, the texture mapper 43 and the blender 29 to request processing operations by those graphic specific accelerators. In addition to this, these graphics-specific accelerators are also able to communicate directly with each other and with the thread spawner 40, independently of the programmable execution unit 41. This allows for certain graphics processing operations to be performed using direct communication between the graphics-specific accelerators of the graphics processing unit, instead of executing instructions in the programmable execution unit to trigger the performance of those operations by the graphics-specific accelerators.
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公开(公告)号：US20180217934A1
公开(公告)日：2018-08-02
申请号：US15423497
申请日：2017-02-02
Applicant: ARM Limited
Inventor： Andreas Due Engh-Halstvedt , Edvard Fielding
IPC: G06F12/0868 , G06F12/0875 , G06F12/0891 , G06F12/0897
CPC classification number: G06F12/0897 , G06F12/0875 , G06F12/126 , G06F12/128 , G06F2212/1016 , G06F2212/302 , G06F2212/455
Abstract: When a data processing operation requires data that is stored in a first cache and the fetching of the data into the first cache is dependent upon data stored in another cache, and an attempt to read the data from the first cache “misses”, the data processing operation is added to a record of data processing operations that have missed in the first cache and the data that is required for the data processing operation is fetched into the first cache by reading the data that is required to fetch the data into the first cache from the another cache and then using that data from the another cache to fetch the required data into the first cache. When the data that is required for the data processing operation has been fetched into the first cache, the data processing operation is performed using the fetched data.
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公开(公告)号：US10013790B2
公开(公告)日：2018-07-03
申请号：US15042540
申请日：2016-02-12
Applicant: ARM Limited
Inventor： Sandeep Kakarlapudi , Andreas Due Engh-Halstvedt , Lars Oskar Flordal , Arne Bergene Fossaa
CPC classification number: G06T15/005 , G06T11/40
Abstract: In a graphics processing system, a driver for the graphics processing pipeline can include conditional graphics processing tasks in the graphics processing tasks that are to be executed by the graphics processing pipeline to generate a render output required by an application. Each such conditional task has associated with it a condition to be used by the graphics processing pipeline to determine whether to execute processing for the task or not and a region of the render output over which the processing for the task will be executed when the condition for the task is met. The graphics processing pipeline determines whether the condition associated with the task has been met, and only executes the processing for the task if the condition associated with the task has been met.
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