Abstract:
A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method comprises: S1: sequentially forming an active layer (3), a gate insulation layer (4), a gate electrode (5) and an interlayer insulation layer (6) on a base substrate (1); S2: forming a first metal thin film layer (8); S3: performing a hydrogenation treatment on the active layer (3) and the gate insulation layer (6); S4: forming a second metal thin film layer (7), the second metal thin film layer (7) being used for forming a source electrode and a drain electrode.
Abstract:
An array substrate and a display. A peripheral region of the array substrate includes a data selector circuit. The data selector circuit includes a plurality of selection driving transistors arranged in a row direction and a column direction, and each selection driving transistor includes a semiconductor layer, a source electrode and a drain electrode. The source electrode is connected to the semiconductor layer through source via holes, and the drain electrode is connected to the semiconductor layer through drain via holes. A minimum distance between the channel region and an edge of the source via hole furthest from the channel region is greater than a minimum distance between the channel region and an outer edge of the source electrode. An acute included angle is formed between the row direction and a line connecting centers of the source via hole and the drain via hole.
Abstract:
An electrostatic protection circuit and a manufacturing method thereof, an array substrate, and a display device are provided. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line.
Abstract:
A touch display panel is disclosed, which includes components of a conventional touch display panel, and further includes: first leads and first data lines share a first test signal line, second leads and second data lines share a second test signal line: and first touch test switches for controlling the first leads and first data test switches for controlling the first data lines are not simultaneously turned on, second touch test switches for controlling the second leads and second data test switches for controlling the second data lines are not simultaneously turned on.
Abstract:
An array substrate includes a base substrate, a thin film transistor on the base substrate, including a gate electrode connected to a gate line, an active layer, a gate insulating layer insulating the gate electrode from the active layer, a first electrode connected to a data line, and a second electrode spaced apart from the first electrode, and a micro light emitting diode on the base substrate, including a first electrode, a first buffer layer, a light emitting layer, and a second electrode, which are stacked on top of each other. The first buffer layer is in a same layer as the active layer. The second electrode of the thin film transistor is connected to one of the first electrode of the micro light emitting diode or the second electrode of the micro light emitting diode.
Abstract:
The present disclosure discloses an electrostatic protection circuit, an array substrate and a display device. In an actual application, a first electrostatic discharge end and a second electrostatic discharge end in the electrostatic protection circuit are respectively coupled with electrostatic protection lines such as a common electrode line, a high-potential reference voltage line and a low potential reference voltage line; a signal line connecting end is coupled with signal lines such as a gate line and a data line; and when the voltage generated by the electrostatic charges accumulated on the signal lines is too large or too small the signal lines and the electrostatic protection lines can be conducted through transistors in the first electrostatic discharge circuit or in the second electrostatic discharge circuit, so that effective electrostatic discharge of the signal lines in a product can be realized without influencing the realization of normal functions of the product.
Abstract:
An array substrate includes a base substrate, at least one first signal line and at least one second signal line disposed at a first side of the base substrate, and at least one electrostatic discharge (ESD) protection device disposed at the first side of the base substrate. Each ESD protection device includes a first electrode coupled to one first signal line, a second electrode coupled to one second signal line, and an insulating medium disposed between the first electrode and the second electrode. An orthographic projection of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the second electrode on the base substrate, and the ESD protection device is configured to discharge electrostatic charges on one of the first signal line and the second signal line that are coupled to the ESD protection device to the other one.
Abstract:
The present disclosure provides a package structure of a display component and a display device. The package structure of a display component includes: a base substrate, a display component arranged on a surface of the base substrate, and an package layer covering the display component, in which the package layer includes a second inorganic layer, an organic layer, and a first inorganic layer capable of reducing amount of charges to be trapped sequentially stacked along a direction toward the display component.
Abstract:
The present disclosure provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a plurality of pixel units arranged in a matrix, each the pixel unit includes a plurality of pixel regions, each pixel region is provided with a display electrode having a slit; a plurality of data lines, each of the data lines includes a plurality of data line segments, any two adjacent data line segments are electrically coupled to each other; in each of the pixel units, each of a part of the pixel regions has a display electrode whose slit is parallel to a data line segment adjacent to this display electrode in the data lines; each of another part of the pixel regions has a display electrode whose slit is non-parallel to a data line segment adjacent to this display electrode in the data lines.
Abstract:
The application discloses an array substrate, comprising a base, a conductive pattern layer disposed on the base, a transparent electrode layer, and an insulating layer disposed between the conductive pattern layer and the transparent electrode layer, the conductive pattern layer comprises a plurality of first conductive patterns, the transparent electrode layer comprises a plurality of transparent electrodes, each of the transparent electrodes is electrically coupled to a corresponding one of the first conductive patterns through a corresponding via hole in the insulating layer, wherein at a position where at least one via hole is located, a stepped structure is formed between the first conductive pattern corresponding to the via hole and the base and/or the insulating layer such that a groove is formed at an upper surface of the array substrate at a position corresponding to the via hole. The application further discloses a display device.