Shift register, gate driving circuit and relevant display device

    公开(公告)号:US09799272B2

    公开(公告)日:2017-10-24

    申请号:US15320613

    申请日:2016-02-05

    Abstract: There are provided a shift register, a gate driving circuit and a relevant display device, comprising a first node controlling module (1), a second node controlling module (2), a third node controlling module (3), a first outputting module (4) and a second outputting module (5). The first node controlling module (1) adjust a potential of a first node (A), the second node controlling module (2) adjust a potential of a second node (B), the third node controlling module (3) adjust a potential of a third node (C), the first outputting module (4) adjust a potential of a driving signal output terminal (Output), and the second outputting module (5) adjusts the potential of the driving signal output terminal (Output). Through mutual coordination of the five modules, the shift register could control a time length of a scanning signal outputted by the driving signal output terminal (Output) by only changing a time length of an input signal (Input), without changing clock signals (CK,CB) and changing the circuit and process, so that difficulty of the gate driving circuit and complexity of process could be reduced, thereby the cost is reduced.

    Display panel, display device, and method of manufacturing display panel

    公开(公告)号:US12295212B2

    公开(公告)日:2025-05-06

    申请号:US17353927

    申请日:2021-06-22

    Inventor: Jianchao Zhu

    Abstract: A display panel, a display device, and a method of manufacturing the display panel is disclosed. The display panel includes a plurality of sub-pixel units, each sub-pixel unit includes a first metal layer, a first planarization layer, a first electrode layer, a pixel definition layer, a light-emitting layer, and a second electrode layer that are sequentially stacked in this order, wherein the first metal layer comprises at least one longitudinal wire, the first metal layer, the pixel definition layer, the first electrode layer, and the second electrode layer employ an axial symmetry structure respectively; when the number of the longitudinal wires is odd, a longitudinal wire at center is taken as a symmetry axis of the axial symmetry structure; and when the number of the longitudinal wires is even, a center line between two longitudinal wires at outermost edges is taken as the symmetry axis of the axial symmetry structure.

    Stretchable display panel and display device

    公开(公告)号:US12262607B2

    公开(公告)日:2025-03-25

    申请号:US17631372

    申请日:2021-02-20

    Abstract: A stretchable display panel has a plurality of island regions and a plurality of bridge regions. The island regions are arranged in an array. Every two adjacent island regions are connected with a bridge region in the bridge regions therebetween. The display panel includes a plurality of sub-pixels and a plurality of signal line groups. At least one sub-pixel is provided in each island region. The signal line groups are located in a same conductive layer. Each signal line group extends along bridge regions to island regions that are connected to the bridge regions. The signal line group includes a plurality of signal lines arranged in parallel and at intervals. Each signal line is electrically connected to sub-pixels in the island regions.

    Display substrate, display panel and display device

    公开(公告)号:US12190816B2

    公开(公告)日:2025-01-07

    申请号:US18556403

    申请日:2023-01-29

    Abstract: Provided are a display substrate, a display panel, and a display device. The display substrate includes a base substrate, pixel circuits, groups of data lines, and first power lines. At least one column of pixel circuits is electrically connected to at least one group of data lines and includes first and second pixel circuits alternately arranged in the second direction. The at least one group of data lines includes first and second data lines. For the at least one column of pixel circuits, input transistors of first and second pixel circuits are electrically connected to first and second data lines, respectively. In the first direction, the first data line, the first power line and the second data line are arranged in sequence, and input transistors of first and second pixel circuits are respectively located on a side of the first power line close to the first and second data line.

    Fingerprint identification device, display panel and fabrication method thereof, and display device

    公开(公告)号:US11354927B2

    公开(公告)日:2022-06-07

    申请号:US16472438

    申请日:2018-12-06

    Abstract: A fingerprint identification device, a display panel, a fabrication method thereof, and a display device are disclosed. The fingerprint identification device includes a fingerprint sensor, an aperture diaphragm, and a first shielding structure. The fingerprint sensor includes a plurality of sensing units; the aperture diaphragm is on a light incident side of the fingerprint sensor and includes an aperture through which light is allowed to be incident on at least one sensing unit of the fingerprint sensor; and the first shielding structure is on a side of the aperture diaphragm facing away from the fingerprint sensor, and surrounds at least a portion of the aperture.

    GATE DRIVING CIRCUIT, METHOD FOR IMPLEMENTING GATE DRIVING CIRCUIT, AND METHOD FOR DRIVING GATE DRIVING CIRCUIT

    公开(公告)号:US20200035166A1

    公开(公告)日:2020-01-30

    申请号:US16398762

    申请日:2019-04-30

    Abstract: The embodiments of the present disclosure disclose a gate driving circuit. The gate driving circuit includes at least one stage of shift register unit to be compensated, wherein a driving terminal of each stage of shift register unit to be compensated is connected to a gate line of a corresponding row of pixels to be compensated, and at least one stage of parasitics compensation circuit, wherein each stage of parasitics compensation circuit is connected in series between a power supply line and a driving terminal of a corresponding shift register unit to be compensated. Each stage of parasitics compensation circuit is configured to compensate a driving terminal of a corresponding shift register unit to be compensated for parasitic capacitance and/or parasitic resistance, so that respective stages of shift register units to be compensated have the same driving load.

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