公开(公告)号：US20140241411A1

公开(公告)日：2014-08-28

申请号：US13852398

申请日：2013-03-28

Applicant: BROADCOM CORPORATION

Inventor： Ali Ghiasi

IPC: H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/4904

Abstract: A system and method for link training of a backplane physical layer device operating in simplex mode. In one embodiment of the present invention, a backplane training system includes a backplane device coupled to a first end of a backplane and at least one retimer device at a second end of the backplane. During a training process, a receiving device is configured to forward a training frame (e.g., DME frame) to a second device for use by a transmitter in the second device.

Abstract translation: 用于单工模式下工作的背板物理层设备的链路训练的系统和方法。 在本发明的一个实施例中，背板训练系统包括耦合到背板的第一端的底板装置和在背板的第二端处的至少一个重定时器装置。 在训练过程中，接收设备被配置为将训练帧（例如，DME帧）转发到第二设备以供第二设备中的发射机使用。

公开(公告)号：US20130243072A1

公开(公告)日：2013-09-19

申请号：US13871831

申请日：2013-04-26

Applicant: BROADCOM CORPORATION

Inventor： Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

IPC: H04L27/00

CPC classification number: H04L27/0002 ,  H04B1/0007 ,  H04B1/406

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Abstract translation: 根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作 。

公开(公告)号：US20130058363A1

公开(公告)日：2013-03-07

申请号：US13668517

申请日：2012-11-05

Applicant: Broadcom Corporation

Inventor： Ali Ghiasi

IPC: H04J3/06

CPC classification number: H04L49/357 ,  H04L49/3054

Abstract: Systems, apparatuses and methods are disclosed for using elastic buffers in fibre channel systems over twisted pair links. One such system includes a fibre channel host device and another fibre channel host device communicatively coupled to the fibre channel device over a twisted pair link. The system also includes a slave physical layer (PHY) circuit residing in the fibre channel host device and a master PHY circuit residing in the another fibre channel host device. The master PHY circuit is operable to transmit, using a reference clock, data from a transmit elastic buffer. The slave PHY circuit is operable to receive the data transmitted by the master PHY circuit and to store the received data using a derived clock recovered from the received data.

Abstract translation: 公开了在双绞线链路上在光纤通道系统中使用弹性缓冲器的系统，装置和方法。 一种这样的系统包括光纤通道主机设备和通过双绞线链路通信地耦合到光纤通道设备的另一光纤通道主机设备。 该系统还包括驻留在光纤通道主机设备中的从属物理层（PHY）电路和驻留在另一光纤通道主机设备中的主PHY电路。 主PHY电路可操作以使用参考时钟从发送弹性缓冲器发送数据。 从PHY电路可操作以接收主PHY电路发送的数据，并使用从接收到的数据恢复的导出时钟来存储接收的数据。

公开(公告)号：US09143464B2

公开(公告)日：2015-09-22

申请号：US13668517

申请日：2012-11-05

Applicant: Broadcom Corporation

Inventor： Ali Ghiasi

IPC: H04L12/931 ,  H04L12/935

CPC classification number: H04L49/357 ,  H04L49/3054

Abstract: Systems, apparatuses and methods are disclosed for using elastic buffers in fiber channel systems over twisted pair links. One such system includes a fiber channel host device and another fiber channel host device communicatively coupled to the fiber channel device over a twisted pair link. The system also includes a slave physical layer (PHY) circuit residing in the fiber channel host device and a master PHY circuit residing in the another fiber channel host device. The master PHY circuit is operable to transmit, using a reference clock, data from a transmit elastic buffer. The slave PHY circuit is operable to receive the data transmitted by the master PHY circuit and to store the received data using a derived clock recovered from the received data.

Abstract translation: 公开了在双绞线链路上在光纤通道系统中使用弹性缓冲器的系统，装置和方法。 一种这样的系统包括光纤通道主机设备和通过双绞线链路通信地耦合到光纤通道设备的另一光纤通道主机设备。 该系统还包括驻留在光纤通道主机设备中的从属物理层（PHY）电路和驻留在另一光纤通道主机设备中的主PHY电路。 主PHY电路可操作以使用参考时钟从发送弹性缓冲器发送数据。 从PHY电路可操作以接收主PHY电路发送的数据，并使用从接收到的数据恢复的导出时钟来存储接收的数据。

公开(公告)号：US20140241369A1

公开(公告)日：2014-08-28

申请号：US13853164

申请日：2013-03-29

Applicant: BROADCOM CORPORATION

Inventor： Ali Ghiasi

IPC: H04L12/861

CPC classification number: H04L49/9057

Abstract: A system and method for data flow identification and alignment in a 40/100 gigabit Ethernet gearbox. Virtual lane (VL) identifiers can be identified to create an effective wiring diagram for data flows. This wiring diagram enables a multiplexer or de-multiplexer to align the VL identifiers to match physical lane identifiers.

Abstract translation: 一种用于40/100千兆以太网变速箱中的数据流识别和对准的系统和方法。 可以识别虚拟通道（VL）标识符，以创建数据流的有效接线图。 该接线图使多路复用器或解复用器能够使VL标识符对准物理通道标识符。