Abstract:
Certain aspects of a method and system for speed negotiation for twisted pair links in fiber channel systems are disclosed. Aspects of a method may include communicating data between fiber channel host devices communicatively coupled via a twisted pair link based on a common speed negotiated between the fiber channel host devices. At least one available speed may be determined for the communication of data between the fiber channel host devices over the twisted pair link. The determined available speeds for each of the fiber channel host devices may be exchanged via at least one fast link pulse signal. The common speed negotiated may be a highest available speed for the communication of data between the fiber channel host devices.
Abstract:
A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox.
Abstract:
A system and method for data flow identification and alignment in a 40/100 gigabit Ethernet gearbox. Virtual lane (VL) identifiers can be identified to create an effective wiring diagram for data flows. This wiring diagram enables a multiplexer or de-multiplexer to align the VL identifiers to match physical lane identifiers.
Abstract:
Disclosed are various embodiments for in-band management of Ethernet links utilizing a bit-interleaved parity (BIP) block in a transmission frame. According to various embodiments, a bit-interleaved parity error code may be generated for a monitored portion of network data for transmission in a first bit-interleaved parity block. Subsequently, network management data may be encoded in a plurality of bits for transmission in a second bit-interleaved parity block according to a predefined block code, wherein the predefined block code generates the plurality of bits to maintain a DC balance between the bit-interleaved parity error code and the plurality of bits.
Abstract:
According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.
Abstract:
A system and method for system and method for 10/40 gigabit Ethernet multi-lane gearbox. In one embodiment, a gearbox device includes one or more inputs on a line side of the device, the one or more inputs being configured to receive four asynchronous 10 Gbit/s Ethernet channels, a marking module that is configured to insert virtual lane markers into four data flows at defined intervals to produce four marked data flows, and a 4:n physical media attachment (PMA) module that is configured to generate one or more higher-rate data flows based on the four marked data flows.
Abstract:
Certain aspects of a method and system for speed negotiation for twisted pair links in fibre channel systems are disclosed. Aspects of a method may include communicating data between fibre channel host devices communicatively coupled via a twisted pair link based on a common speed negotiated between the fibre channel host devices. At least one available speed may be determined for the communication of data between the fibre channel host devices over the twisted pair link. The determined available speeds for each of the fibre channel host devices may be exchanged via at least one fast link pulse signal. The common speed negotiated may be a highest available speed for the communication of data between the fibre channel host devices.
Abstract:
Disclosed are various embodiments for in-band management of Ethernet links utilizing a bit-interleaved parity (BIP) block in a transmission frame. According to various embodiments, a bit-interleaved parity error code may be generated for a monitored portion of network data for transmission in a first bit-interleaved parity block. Subsequently, network management data may be encoded in a plurality of bits for transmission in a second bit-interleaved parity block according to a predefined block code, wherein the predefined block code generates the plurality of bits to maintain a DC balance between the bit-interleaved parity error code and the plurality of bits.
Abstract:
A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox.
Abstract:
A system and method for 10/40 gigabit Ethernet multi-lane gearbox. In one embodiment, a gearbox device includes one or more inputs on a line side of the device, the one or more inputs being configured to receive four asynchronous 10 Gbit/s Ethernet channels, a marking module that is configured to insert virtual lane markers into four data flows at defined intervals to produce four marked data flows, and a 4:n physical media attachment (PMA) module that is configured to generate one or more higher-rate data flows based on the four marked data flows.