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    DATA AND KEY SEPARATION USING A SECURE CENTRAL PROCESSING UNIT
    11.
    发明申请
    DATA AND KEY SEPARATION USING A SECURE CENTRAL PROCESSING UNIT 有权
    使用安全中央处理单元的数据和关键分离

    公开(公告)号：US20140053278A1

    公开(公告)日：2014-02-20

    申请号：US13707050

    申请日：2012-12-06

    Applicant: BROADCOM CORPORATION

    Inventor： Andrew Dellow ,  Shashank Shekhar ,  Stephane Rodgers

    IPC: G06F21/60

    CPC classification number: G06F21/60 ,  G06F21/575 ,  G06F21/602 ,  G06F21/74 ,  G06F21/78 ,  G06F2221/2107 ,  G06F2221/2113 ,  H04L9/0838 ,  H04N5/4401 ,  H04N21/426 ,  H04N21/4408 ,  H04N21/4627

    Abstract: A computing system, comprising includes a first central processing unit (CPU) and a second CPU coupled with the first CPU and with a host processor. The second CPU and the host processor may both request the first CPU to generate keys that have access rights to regions of memory to access specific data. The first CPU may be configured to, in response to a request from the second CPU, generate a unique key with a unique access right to a region of memory, the unique key usable only by the second CPU, not the host processor.

    Abstract translation: 一种计算系统，包括第一中央处理单元（CPU）和与第一CPU耦合的第二CPU和主机处理器。 第二CPU和主机处理器都可以请求第一CPU产生具有对存储器区域的访问权限的密钥以访问特定数据。 第一CPU可以被配置为响应于来自第二CPU的请求，生成具有对存储器区域的唯一访问权限的唯一密钥，唯一密钥仅可由第二CPU而不是主机处理器使用。

    Security Central Processing Unit Monitoring of On-Chip Conditions
    14.
    发明申请
    Security Central Processing Unit Monitoring of On-Chip Conditions 有权
    安全中央处理单元监控片上条件

    公开(公告)号：US20140053259A1

    公开(公告)日：2014-02-20

    申请号：US13675808

    申请日：2012-11-13

    Applicant: BROADCOM CORPORATION

    Inventor： Stephane Rodgers

    IPC: G06F21/70 ,  G06F21/50

    CPC classification number: G06F21/81 ,  G06F21/755

    Abstract: A system includes a security processing unit to monitor inputs from process, voltage and temperature sensors to maintain a security of the system. The security processing unit can operate at a determined clock frequency. A timing path detector can connect with the security processing unit. The timing path detector can monitor a condition near the security processing unit. The timing path detector can switch the clock frequency to a lower frequency before the security processing unit fails from the condition.

    Abstract translation: 系统包括一个安全处理单元，用于监视来自过程，电压和温度传感器的输入，以保持系统的安全性。 安全处理单元可以以确定的时钟频率工作。 定时路径检测器可以与安全处理单元连接。 定时路径检测器可以监视安全处理单元附近的状况。 定时路径检测器可以在安全处理单元从该条件失败之前将时钟频率切换到较低的频率。

    MULTI-SECURITY-CPU SYSTEM
    15.
    发明申请
    MULTI-SECURITY-CPU SYSTEM 有权
    多安全CPU系统

    公开(公告)号：US20140053230A1

    公开(公告)日：2014-02-20

    申请号：US13705991

    申请日：2012-12-05

    Applicant: BROADCOM CORPORATION

    Inventor： Stephane Rodgers ,  Andrew Dellow

    IPC: G06F21/00

    CPC classification number: G06F21/123 ,  G06F21/72 ,  G06F21/74 ,  G06F2221/2113

    Abstract: A computing system includes a first security central processing unit (SCPU) of a system-on-a-chip (SOC), the first SCPU configured to execute functions of a first security level. The computing system also includes a second SCPU of the SOC coupled with the first SCPU and coupled with a host processor, the second SCPU configured to execute functions of a second security level less secure than the first security level, and the second SCPU executing functions not executed by the first SCPU.

    Abstract translation: 计算系统包括片上系统（SOC）的第一安全中央处理单元（SCPU），第一SCPU被配置为执行第一安全级别的功能。 计算系统还包括与第一SCPU耦合并与主处理器耦合的SOC的第二SCPU，第二SCPU被配置为执行比第一安全级别更不安全的第二安全级别的功能，而第二SCPU执行功能不是 由第一个SCPU执行。

    PROTECTING SECURE SOFTWARE IN A MULTI-SECURITY-CPU SYSTEM
    16.
    发明申请
    PROTECTING SECURE SOFTWARE IN A MULTI-SECURITY-CPU SYSTEM 有权
    在多个安全CPU系统中保护安全软件

    公开(公告)号：US20140052975A1

    公开(公告)日：2014-02-20

    申请号：US13707023

    申请日：2012-12-06

    Applicant: BROADCOM CORPORATION

    Inventor： Stephane Rodgers ,  Shashank Shekhar

    IPC: G06F21/60

    CPC classification number: G06F21/602 ,  G06F21/575

    Abstract: A computing system includes a first central processing unit (CPU) and a second CPU coupled with the first CPU and with a host processor. In response to a request by the host processor to boot the second CPU, the first CPU is configured to execute secure booting of the second CPU by decrypting encrypted code to generate decrypted code executable by the second CPU but that is inaccessible by the host processor.

    Abstract translation: 计算系统包括与第一CPU并与主处理器耦合的第一中央处理单元（CPU）和第二CPU。 响应于主机处理器引导第二CPU的请求，第一CPU被配置为通过解密加密代码来执行第二CPU的安全引导，以生成可由第二CPU执行但是由主机处理器无法访问的解密代码。

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