公开(公告)号：US20080205112A1

公开(公告)日：2008-08-28

申请号：US11678097

申请日：2007-02-23

Applicant: David C. Lawson ,  Jason Ross

Inventor： David C. Lawson ,  Jason Ross

IPC: G11C5/06

CPC classification number: G11C11/4125

Abstract: A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first inverter and a second inverter connected to each other in a cross-coupled manner. The SEU hardened memory cell also includes a first resistor, a second resistor and a capacitor. The first resistor is connected between an input of the first inverter and an output of the second inverter. The second resistor is connected between an input of the second inverter and an output of the first inverter. The capacitor is connected between an input of the first inverter and an input of the second inverter.

Abstract translation: 公开了在静态随机存取存储器中使用的单个事件镦粗（SEU）硬化存储单元。 SEU硬化存储单元包括以交叉耦合方式彼此连接的第一反相器和第二反相器。 SEU硬化存储单元还包括第一电阻器，第二电阻器和电容器。 第一电阻器连接在第一反相器的输入端和第二反相器的输出端之间。 第二电阻器连接在第二反相器的输入端和第一反相器的输出端之间。 电容器连接在第一反相器的输入端和第二反相器的输入端之间。

公开(公告)号：US07307948B2

公开(公告)日：2007-12-11

申请号：US10278189

申请日：2002-10-21

Applicant: Jon L. Infante ,  Mark J. Karnowski ,  Christopher Carlin ,  David C. Lawson

Inventor： Jon L. Infante ,  Mark J. Karnowski ,  Christopher Carlin ,  David C. Lawson

IPC: G01R31/08 ,  G06F11/00 ,  G06F15/16 ,  G06F3/00 ,  H04L1/00 ,  H04L12/28 ,  H04L12/56

CPC classification number: G06F11/2007 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0635 ,  G06F3/067 ,  G06F11/2005

Abstract: A system comprising a host system, a driver in communication with a host system, and a plurality of host bus adapters in communication with the driver. The host bus adapters provide a plurality of data transmission paths between the host system and a storage device. The driver is operable to adjust data transmission loads between the paths without burdening the operating system.

Abstract translation: 一种包括主机系统，与主机系统通信的驱动器以及与所述驱动器通信的多个主机总线适配器的系统。 主机总线适配器在主机系统和存储设备之间提供多个数据传输路径。 驱动器可操作以在路径之间调整数据传输负载，而不会对操作系统造成负担。

公开(公告)号：US06301179B1

公开(公告)日：2001-10-09

申请号：US09570064

申请日：2000-05-12

Applicant: David C. Lawson

Inventor： David C. Lawson

IPC: G11C700

CPC classification number: G11C7/067 ,  G11C11/419

Abstract: In a sense amplifier for reading out memory cells of a memory comprising a set of P-FETs and N-FETs, complementary input signals received from the memory cell being read out are applied to input junctions connected to gates of N-FETs. The input junctions are charged to 0.8 volts by a precharging circuit comprising P-FETs connecting the input junctions to ground and an N-FET shunting the input junctions together. The P-FETs and N-FETs of the precharging circuit are rendered conductive between memory cells readouts to precharge the input junctions and are rendered nonconducting during memory cell readouts. A second precharging circuit precharges an output junction of the sense amplifier circuit. The output junction is connected to an output amplification stage including a CMOS circuit. Because of the low equalization voltage to which the input junctions are precharged, the time to precharge the input junctions is dramatically reduced and a reduction in the memory access time is achieved.

Abstract translation: 在用于读出包含一组P-FET和N-FET的存储器的存储单元的读出放大器中，从读出的存储单元接收的互补输入信号被施加到与N-FET的栅极连接的输入结。 通过包括将输入结连接到地的P-FET的预充电电路将输入结充电到0.8伏，并将N-FET将输入结分流在一起。 预充电电路的P-FET和N-FET在存储器单元读出之前被导通，以对输入结进行预充电，并且在存储器单元读出期间变为非导通。 第二预充电电路对读出放大器电路的输出结进行预充电。 输出端连接到包括CMOS电路的输出放大级。 由于输入接点预充电的低均衡电压，大大降低了对输入接点进行预充电的时间，并且实现了存储器访问时间的减少。