-
公开(公告)号：US07904697B2
公开(公告)日：2011-03-08
申请号：US12044013
申请日：2008-03-07
CPC分类号： G06F9/30032 , G06F9/384
摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.
摘要翻译： 一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。 在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。 当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。 并且通过这个任务，别名被破坏了。 类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。 并且通过这个任务，别名被破坏了。
-
公开(公告)号：US20090228692A1
公开(公告)日：2009-09-10
申请号：US12044013
申请日：2008-03-07
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/384
摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.
摘要翻译： 一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。 在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。 当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。 并且通过这个任务，别名被破坏了。 类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。 并且通过这个任务，别名被破坏了。
-
13.发明授权公开(公告)号：US07130947B2
公开(公告)日：2006-10-31
申请号：US10835349
申请日：2004-04-29
申请人： Brian David Barrick
发明人： Brian David Barrick
CPC分类号： G06F13/364
摘要： The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of low-speed requesters generate requests every two full-speed cycles, and hold their requests for two full-speed cycles. The arbitration method gives priority to the requests from the low-priority requesters and guarantees that two requests made by the half-speed requestors at the beginning of a low-speed cycle will be granted over the course of the low-speed cycle. The requests generated by the low-speed requestors are issued in phases. Issuance of later phases of a request is blocked when the request has been granted in an earlier phase.
摘要翻译： 本发明提供了一种允许来自多个频域的请求者的资源的仲裁方法。 大多数请求者全速生成请求。 少数低速请求者每两个全速循环产生请求，并保持两个全速循环的请求。 仲裁方法优先考虑来自低优先级请求者的请求，并保证半速请求者在低速周期开始时作出的两个请求将在低速周期的过程中被授予。 低速请求者产生的请求分阶段发布。 当请求在较早阶段被授予时，发出请求的后续阶段将被阻止。
-
14.发明授权公开(公告)号：US06895454B2
公开(公告)日：2005-05-17
申请号：US09981879
申请日：2001-10-18
申请人： Brian David Barrick
发明人： Brian David Barrick
CPC分类号： G06F9/546
摘要： A method and an apparatus for sharing a request queue between two or more destinations. The method and apparatus utilizes a common data table and a common age queue. The age queue is used to select the oldest request. The corresponding request from the common data table is then extracted and sent to the appropriate destination.
摘要翻译： 一种在两个或多个目的地之间共享请求队列的方法和装置。 该方法和装置利用公共数据表和公共年龄队列。 年龄队列用于选择最旧的请求。 然后提取来自公共数据表的相应请求并将其发送到适当的目的地。
-
15.发明授权Method of analyzing and filtering timing runs using common timing characteristics 有权使用公共时序特征分析和过滤定时运行的方法公开(公告)号：US06779162B2
公开(公告)日：2004-08-17
申请号：US10042101
申请日：2002-01-07
申请人： Brian David Barrick , Alvan Wing Ng
发明人： Brian David Barrick , Alvan Wing Ng
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method of analyzing timing reports in a microprocessor design for quick identification of all negative timing paths has been provided. Timing paths are first grouped and saved in a list file. A timing analysis program searches the timing report file for timing paths that match those in the list file. Summary reports have been generated for the existing timing paths. If there are new timing paths, summary reports for the new timing paths are generated. The new timing paths go through the same procedure until all negative timing paths are identified.
摘要翻译： 已经提供了一种分析微处理器设计中的定时报告以快速识别所有负定时路径的方法。 时序路径首先分组并保存在列表文件中。 定时分析程序在定时报告文件中搜索与列表文件中匹配的定时路径。 已经为现有的时序路径生成了摘要报告。 如果有新的定时路径，则会生成新的时序路径的汇总报告。 新的定时路径通过相同的过程，直到识别出所有负时序路径。
-
-
-
-
搜索结果
15 条记录 (耗时 0.021 秒)