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15 条记录 (耗时 0.018 秒)

    Programmable data prefetch pacing
    1.
    发明授权
    Programmable data prefetch pacing 失效
    可编程数据预取起搏

    公开(公告)号：US06578130B2

    公开(公告)日：2003-06-10

    申请号：US09981880

    申请日：2001-10-18

    申请人： Brian David Barrick ,  Michael John Mayfield ,  Brian Patrick Hanley

    发明人： Brian David Barrick ,  Michael John Mayfield ,  Brian Patrick Hanley

    IPC分类号： G06F1200

    CPC分类号： G06F12/0897 ,  G06F12/0862

    摘要： A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to determine if additional prefetches should currently be performed. By limiting the number of prefetches being performed at any given time, the use of system resources for prefetching can be controlled, and thus system performance can be optimized.

    摘要翻译： 一种用于在计算机系统中预取数据的方法和装置，其跟踪当前活动的预取数，并将该数量与预设的最大允许预取数量进行比较，以确定是否应当执行附加预取。 通过限制在任何给定时间执行的预取数量，可以控制用于预取的系统资源的使用，从而可以优化系统性能。

    Method of updating cache state information where stores only read the cache state information upon entering the queue
    4.
    发明授权
    Method of updating cache state information where stores only read the cache state information upon entering the queue 失效
    更新高速缓存状态信息的方法，其中存储仅在进入队列时读取高速缓存状态信息

    公开(公告)号：US07302530B2

    公开(公告)日：2007-11-27

    申请号：US10897348

    申请日：2004-07-22

    申请人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai

    发明人： Brian David Barrick ,  Dwain Alan Hicks ,  Takeki Osanai

    IPC分类号： G06F12/08

    CPC分类号： G06F9/3834 ,  G06F12/0815 ,  G06F12/0855

    摘要： The present invention provides a method of updating the cache state information for store transactions in an system in which store transactions only read the cache state information upon entering the unit pipe or store portion of the store/load queue. In this invention, store transactions in the unit pipe and queue are checked whenever a cache line is modified, and their cache state information updated as necessary. When the modification is an invalidate, the check tests that the two share the same physical addressable location. When the modification is a validate, the check tests that the two involve the same data cache line.

    摘要翻译： 本发明提供了一种在系统中更新用于存储事务的高速缓存状态信息的方法，其中存储事务仅在进入存储/加载队列的单元管道或存储部分时才读取高速缓存状态信息。 在本发明中，每当修改高速缓存行时检查单元管道和队列中的事务，并根据需要更新其缓存状态信息。 当修改无效时，检查测试两个共享相同的物理可寻址位置。 当修改是有效的，检查测试两个涉及相同的数据高速缓存行。

    Load register instruction short circuiting method
    5.
    发明授权
    Load register instruction short circuiting method 有权
    加载寄存器指令短路方式

    公开(公告)号：US07904697B2

    公开(公告)日：2011-03-08

    申请号：US12044013

    申请日：2008-03-07

    申请人： Brian David Barrick ,  Brian William Curran ,  Lee Evan Eisen

    发明人： Brian David Barrick ,  Brian William Curran ,  Lee Evan Eisen

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44

    CPC分类号： G06F9/30032 ,  G06F9/384

    摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.

    摘要翻译： 一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。 在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。 当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。 并且通过这个任务，别名被破坏了。 类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。 并且通过这个任务，别名被破坏了。

    Systems for executing load instructions that achieve sequential load consistency
    6.
    发明授权
    Systems for executing load instructions that achieve sequential load consistency 失效
    用于执行实现顺序负载一致性的加载指令的系统

    公开(公告)号：US07730290B2

    公开(公告)日：2010-06-01

    申请号：US12036992

    申请日：2008-02-25

    申请人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/383 ,  G06F12/0855

    摘要： A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

    摘要翻译： 公开了一种用于执行加载指令的方法。 加载指令的地址信息用于生成所需数据的地址，该地址用于搜索所需数据的高速缓冲存储器。 如果在高速缓冲存储器中找到所需的数据，则产生高速缓存命中信号。 地址的至少一部分用于在队列中搜索指定相同地址的先前加载指令。 如果找到指定相同地址的先前加载指令，则忽略缓存命中信号，并将加载指令存储在队列中。 还描述了加载/存储单元和实现该方法的处理器。

    Load Register Instruction Short Circuiting Method
    7.
    发明申请
    Load Register Instruction Short Circuiting Method 有权
    加载寄存器指令短路方法

    公开(公告)号：US20090228692A1

    公开(公告)日：2009-09-10

    申请号：US12044013

    申请日：2008-03-07

    申请人： Brian David Barrick ,  Brian William Curran ,  Lee Evan Eisen

    发明人： Brian David Barrick ,  Brian William Curran ,  Lee Evan Eisen

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/384

    摘要： An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.

    摘要翻译： 一种用于执行加载寄存器指令的装置和方法，其中将负载寄存器指令的源数据保留在其原始物理寄存器中，同时将架构化目标寄存器映射到同一物理目标寄存器。 在这种状态下，两个架构的寄存器对一个物理寄存器进行了别名。 当加载地址指令的源寄存器被指定为后续指令的目标地址时，将自由物理寄存器分配给加载寄存器源寄存器。 并且通过这个任务，别名被破坏了。 类似地，当加载地址指令的目标寄存器是后续指令的目标地址时，新的物理寄存器被分配给加载寄存器目标地址。 并且通过这个任务，别名被破坏了。

    Method of arbitration which allows requestors from multiple frequency domains
    8.
    发明授权
    Method of arbitration which allows requestors from multiple frequency domains 失效
    允许来自多个频域的请求者的仲裁方法

    公开(公告)号：US07130947B2

    公开(公告)日：2006-10-31

    申请号：US10835349

    申请日：2004-04-29

    申请人： Brian David Barrick

    发明人： Brian David Barrick

    IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F13/00

    CPC分类号： G06F13/364

    摘要： The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of low-speed requesters generate requests every two full-speed cycles, and hold their requests for two full-speed cycles. The arbitration method gives priority to the requests from the low-priority requesters and guarantees that two requests made by the half-speed requestors at the beginning of a low-speed cycle will be granted over the course of the low-speed cycle. The requests generated by the low-speed requestors are issued in phases. Issuance of later phases of a request is blocked when the request has been granted in an earlier phase.

    摘要翻译： 本发明提供了一种允许来自多个频域的请求者的资源的仲裁方法。 大多数请求者全速生成请求。 少数低速请求者每两个全速循环产生请求，并保持两个全速循环的请求。 仲裁方法优先考虑来自低优先级请求者的请求，并保证半速请求者在低速周期开始时作出的两个请求将在低速周期的过程中被授予。 低速请求者产生的请求分阶段发布。 当请求在较早阶段被授予时，发出请求的后续阶段将被阻止。

    SYSTEMS FOR EXECUTING LOAD INSTRUCTIONS THAT ACHIEVE SEQUENTIAL LOAD CONSISTENCY
    9.
    发明申请
    SYSTEMS FOR EXECUTING LOAD INSTRUCTIONS THAT ACHIEVE SEQUENTIAL LOAD CONSISTENCY 失效
    执行顺序负载一致的负载指令系统

    公开(公告)号：US20080148017A1

    公开(公告)日：2008-06-19

    申请号：US12036992

    申请日：2008-02-25

    申请人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    发明人： Brian David Barrick ,  Kimberly Marie Fernsler ,  Dwain A. Hicks ,  Takeki Osanai ,  David Scott Ray

    IPC分类号： G06F9/312

    CPC分类号： G06F9/383 ,  G06F12/0855

    摘要： A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

    摘要翻译： 公开了一种用于执行加载指令的方法。 加载指令的地址信息用于生成所需数据的地址，该地址用于搜索所需数据的高速缓冲存储器。 如果在高速缓冲存储器中找到所需的数据，则产生高速缓存命中信号。 地址的至少一部分用于在队列中搜索指定相同地址的先前加载指令。 如果找到指定相同地址的先前加载指令，则忽略缓存命中信号，并将加载指令存储在队列中。 还描述了加载/存储单元和实现该方法的处理器。