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    Method and Apparatus for Evaluating the Timing Effects of Logic Block Location Changes in Integrated Circuit Design
    1.
    发明申请
    Method and Apparatus for Evaluating the Timing Effects of Logic Block Location Changes in Integrated Circuit Design 审中-公开
    用于评估集成电路设计中逻辑块位置变化的时序效应的方法和装置

    公开(公告)号：US20090064068A1

    公开(公告)日：2009-03-05

    申请号：US11848421

    申请日：2007-08-31

    申请人： Alvan Wing Ng ,  Taku Uchino

    发明人： Alvan Wing Ng ,  Taku Uchino

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/84

    摘要： An integrated circuit (IC) floorplan system includes an integration design system that executes IC floorplan software on a semiconductor die IC model. The IC floorplan software includes a timing tool database of the IC model. IC integrators utilize the IC floorplan software to evaluate logic block moves within the IC model. The IC floorplan software analyzes wire interconnect signal propagation time delays that result from prospective logic block moves with the IC model. The IC floorplan software reports back in real time whether or not a prospective move of a logic block from one location to another in the IC model will cause a timing failure due to a wire interconnect time delay exceeding a predetermined timing parameter.

    摘要翻译： 集成电路（IC）楼层规划系统包括在半导体管芯IC模型上执行IC楼层平面图软件的集成设计系统。 IC楼层平面图软件包括IC模型的定时工具数据库。 IC集成商利用IC floorplan软件来评估IC模型内的逻辑块移动。 IC楼层平面图软件分析由IC模型预期逻辑块移动导致的有线互连信号传播时间延迟。 IC楼层规划软件实时回报IC模型中逻辑块从一个位置到另一个位置的预期移动是否会由于超过预定定时参数的电线互连时间延迟而导致定时故障。

    Method and apparatus for operating an age queue for memory request operations in a processor of an information handling system
    4.
    发明授权
    Method and apparatus for operating an age queue for memory request operations in a processor of an information handling system 失效
    用于在信息处理系统的处理器中操作用于存储器请求操作的年龄队列的方法和装置

    公开(公告)号：US07831812B2

    公开(公告)日：2010-11-09

    申请号：US11848492

    申请日：2007-08-31

    申请人： Alvan Wing Ng ,  Takuya Kano

    发明人： Alvan Wing Ng ,  Takuya Kano

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/3824 ,  G06F9/3834 ,  G06F9/3855

    摘要： A processor includes a processor core with a core interface unit that includes an age queue and a request queue. The core interface unit receives load requests from the processor core. The request queue stores the requests in respective slots of the request queue. The age queue stores ID tags in respective age queue slots. Each ID tag in the age queue corresponds to a respective address of a load instruction in the request queue. In one embodiment, ID tags propagate through the age queue at a fixed rate of two at a time from a tail of the age queue to a head of the age queue. Arbitration control circuitry generates an enable bit vector that identifies the oldest ID tag in the age queue corresponding to the oldest load request in the request queue. The arbitration circuitry selects the identified oldest instruction in the request queue as the next to dispatch. In one embodiment, the core interface unit exhibits an input frequency that is a multiple of an internal operating frequency of the core interface unit.

    摘要翻译： 处理器包括具有包括年龄队列和请求队列的核心接口单元的处理器核心。 核心接口单元从处理器核心接收负载请求。 请求队列将请求存储在请求队列的相应时隙中。 年龄队列将ID标签存储在各自的年龄队列插槽中。 年龄队列中的每个ID标签对应于请求队列中的加载指令的相应地址。 在一个实施例中，ID标签以从时间队列的尾部到年龄队列的头部的固定速率以两个固定速率传播通过年龄队列。 仲裁控制电路产生使能位向量，其识别与请求队列中最早的加载请求对应的年龄队列中的最旧的ID标签。 仲裁电路在请求队列中选择已识别的最旧的指令作为发送的下一个指令。 在一个实施例中，核心接口单元呈现出作为核心接口单元的内部工作频率的倍数的输入频率。

    Method of analyzing and filtering timing runs using common timing characteristics
    5.
    发明授权
    Method of analyzing and filtering timing runs using common timing characteristics 有权
    使用公共时序特征分析和过滤定时运行的方法

    公开(公告)号：US06779162B2

    公开(公告)日：2004-08-17

    申请号：US10042101

    申请日：2002-01-07

    申请人： Brian David Barrick ,  Alvan Wing Ng

    发明人： Brian David Barrick ,  Alvan Wing Ng

    IPC分类号： G06F1750

    CPC分类号： G06F17/5031

    摘要： A method of analyzing timing reports in a microprocessor design for quick identification of all negative timing paths has been provided. Timing paths are first grouped and saved in a list file. A timing analysis program searches the timing report file for timing paths that match those in the list file. Summary reports have been generated for the existing timing paths. If there are new timing paths, summary reports for the new timing paths are generated. The new timing paths go through the same procedure until all negative timing paths are identified.

    摘要翻译： 已经提供了一种分析微处理器设计中的定时报告以快速识别所有负定时路径的方法。 时序路径首先分组并保存在列表文件中。 定时分析程序在定时报告文件中搜索与列表文件中匹配的定时路径。 已经为现有的时序路径生成了摘要报告。 如果有新的定时路径，则会生成新的时序路径的汇总报告。 新的定时路径通过相同的过程，直到识别出所有负时序路径。

    Method and Apparatus for Operating an Age Queue for Memory Request Operations in a Processor of an Information Handling System
    7.
    发明申请
    Method and Apparatus for Operating an Age Queue for Memory Request Operations in a Processor of an Information Handling System 失效
    用于在信息处理系统的处理器中操作用于存储器请求操作的年龄队列的方法和装置

    公开(公告)号：US20090063735A1

    公开(公告)日：2009-03-05

    申请号：US11848492

    申请日：2007-08-31

    申请人： Alvan Wing Ng ,  Takuya Kano

    发明人： Alvan Wing Ng ,  Takuya Kano

    IPC分类号： G06F3/00

    CPC分类号： G06F9/3824 ,  G06F9/3834 ,  G06F9/3855

    摘要： A processor includes a processor core with a core interface unit that includes an age queue and a request queue. The core interface unit receives load requests from the processor core. The request queue stores the requests in respective slots of the request queue. The age queue stores ID tags in respective age queue slots. Each ID tag in the age queue corresponds to a respective address of a load instruction in the request queue. In one embodiment, ID tags propagate through the age queue at a fixed rate of two at a time from a tail of the age queue to a head of the age queue. Arbitration control circuitry generates an enable bit vector that identifies the oldest ID tag in the age queue corresponding to the oldest load request in the request queue. The arbitration circuitry selects the identified oldest instruction in the request queue as the next to dispatch. In one embodiment, the core interface unit exhibits an input frequency that is a multiple of an internal operating frequency of the core interface unit.

    摘要翻译： 处理器包括具有包括年龄队列和请求队列的核心接口单元的处理器核心。 核心接口单元从处理器核心接收负载请求。 请求队列将请求存储在请求队列的相应时隙中。 年龄队列将ID标签存储在各自的年龄队列插槽中。 年龄队列中的每个ID标签对应于请求队列中的加载指令的相应地址。 在一个实施例中，ID标签以从时间队列的尾部到年龄队列的头部的固定速率以两个固定速率传播通过年龄队列。 仲裁控制电路产生使能位向量，其识别与请求队列中最早的加载请求对应的年龄队列中的最旧的ID标签。 仲裁电路在请求队列中选择已识别的最旧的指令作为发送的下一个指令。 在一个实施例中，核心接口单元呈现出作为核心接口单元的内部工作频率的倍数的输入频率。

    Fixed snoop response time for source-clocked multiprocessor busses
    8.
    发明授权
    Fixed snoop response time for source-clocked multiprocessor busses 失效
    源时钟多处理器总线的固定侦听响应时间

    公开(公告)号：US07171445B2

    公开(公告)日：2007-01-30

    申请号：US10042103

    申请日：2002-01-07

    申请人： James W. Allen ,  Michael John Mayfield ,  Alvan Wing Ng

    发明人： James W. Allen ,  Michael John Mayfield ,  Alvan Wing Ng

    IPC分类号： G06F1/12 ,  G06F13/40

    CPC分类号： G06F12/0831

    摘要： An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.

    摘要翻译： 在多处理器系统中的一个或多个处理器和存储器控制器中实现接口逻辑。 接口逻辑使得所有处理器能够在将数据提供给较快总线的接收端的本地逻辑之前通过延迟在更快的总线上传输的数据同时接收窥探和窥探响应。 接口逻辑包括连接到存储组件的多路复用器组件的两个或多个路径。 存储组件连接到另一个多路复用器组件，用于选择两个或更多个路径中的一个。 优选地，接收端中的总线控制逻辑确定执行多少延迟以补偿数据总线之间的延迟差。

    Dual-L2 processor subsystem architecture for networking system
    9.
    发明授权
    Dual-L2 processor subsystem architecture for networking system 有权
    用于网络系统的双L2处理器子系统架构

    公开(公告)号：US06751704B2

    公开(公告)日：2004-06-15

    申请号：US09732267

    申请日：2000-12-07

    申请人： Alvan Wing Ng

    发明人： Alvan Wing Ng

    IPC分类号： G06F1200

    CPC分类号： G06F12/0848

    摘要： A method for providing a memory scheme in computer architectures in an efficient and cost effective manner. A processor is configured with access to dual-L2 caches, preferably configured to cache program instructions and data in one cache and shared data in another cache. In one embodiment of the present invention, one L2 cache is accessible to networking interface devices. Optionally, the cache accessible by the networking interface devices is configured as networking buffers, providing cache for packet data being sent within a network. By use of this invention, the packet forwarding speeds in a conventional computer architecture may be increased.

    摘要翻译： 一种以有效和成本有效的方式在计算机体系结构中提供存储器方案的方法。 处理器被配置为访问双L2高速缓存，优选地被配置为在一个高速缓存中缓存程序指令和数据，并且在另一个高速缓存中共享数据。 在本发明的一个实施例中，网络接口设备可以访问一个L2高速缓存。 可选地，由网络接口​​设备访问的高速缓存被配置为网络缓冲区，为在网络内发送的分组数据提供高速缓存。 通过使用本发明，可以增加常规计算机体系结构中的分组转发速度。