公开(公告)号：US20120110532A1

公开(公告)日：2012-05-03

申请号：US12912919

申请日：2010-10-27

申请人： Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David Anthony Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David Anthony Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/62

摘要： A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.

摘要翻译： 一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。 确定第一组多个群集锁存器中的多个组。 添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。 确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。 响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

公开(公告)号：US20120240093A1

公开(公告)日：2012-09-20

申请号：US13047492

申请日：2011-03-14

申请人： Charles Jay Alpert ,  Shiyan Hu ,  Zhuo Li ,  Chin Ngai Sze

发明人： Charles Jay Alpert ,  Shiyan Hu ,  Zhuo Li ,  Chin Ngai Sze

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5077

摘要： A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an application executing in a data processing system, a score is computed for a net in a set of nets routed using a set of layers in the design. The set of nets is sorted according to scores associated with nets in the set of nets. A layer range from a set of layer ranges is assigned to a net in the sorted list such that a net with a higher than threshold score is assigned a high layer range.

摘要翻译： 在说明性实施例中提供了用于在集成电路（IC）的设计中使用层范围的改进路由的方法，系统和计算机程序产品。 使用在数据处理系统中执行的应用程序，计算使用设计中的一组层路由的一组网络中的网络的得分。 网络集合根据与网络集中的网络相关联的分数进行排序。 来自一组层范围的层范围被分配给排序列表中的网，使得具有高于阈值得分的网被分配高层范围。

公开(公告)号：US08677305B2

公开(公告)日：2014-03-18

申请号：US13488065

申请日：2012-06-04

申请人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

发明人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/62

摘要： An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

摘要翻译： 具有接收器定位器单元的电子自动化设计工具基于平衡负载集群中的负载的大小并且基于每个集群的最小延迟，从时钟网络设计的扇区内的多个负载中产生负载集群，以及 在时钟网络设计的扇区中的多个接收器位置中的相应的一个。 该工具确定负载集群的中心，并确定与簇的中心对应的接收位置，以连接扇区缓冲器的输出端点。 每个扇区缓冲器将时钟信号驱动到相应的一组负载。

公开(公告)号：US20130326456A1

公开(公告)日：2013-12-05

申请号：US13488065

申请日：2012-06-04

申请人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

发明人： Charles Jay Alpert ,  Joseph Nicolas Kozhaya ,  Zhuo Li ,  Joseph J Palumbo ,  Haifeng Qian ,  Phillip John Restle ,  Chin Ngai Sze ,  Ying Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/62

摘要： An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

摘要翻译： 具有接收器定位器单元的电子自动化设计工具基于平衡负载集群中的负载的大小并且基于每个集群的最小延迟，从时钟网络设计的扇区内的多个负载中产生负载集群，以及 在时钟网络设计的扇区中的多个接收器位置中的相应的一个。 该工具确定负载集群的中心，并确定与簇的中心对应的接收位置，以连接扇区缓冲器的输出端点。 每个扇区缓冲器将时钟信号驱动到相应的一组负载。

公开(公告)号：US20130086545A1

公开(公告)日：2013-04-04

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US08584070B2

公开(公告)日：2013-11-12

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US20130086544A1

公开(公告)日：2013-04-04

申请号：US13252067

申请日：2011-10-03

申请人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

摘要翻译： 通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。 针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。 在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。 引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。 优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。 阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

公开(公告)号：US08418113B1

公开(公告)日：2013-04-09

申请号：US13252067

申请日：2011-10-03

申请人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

摘要翻译： 通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。 针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。 在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。 引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。 优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。 阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

公开(公告)号：US20120124539A1

公开(公告)日：2012-05-17

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

公开(公告)号：US20120324409A1

公开(公告)日：2012-12-20

申请号：US13162806

申请日：2011-06-17

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

摘要翻译： 通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。 该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。 默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。 作为第二逻辑级中从输出门到第一门的线长度已知特性的函数调整默认转换速率。 基于输入转换速率来计算所选择的门的延迟。 输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。