公开(公告)号：US08584070B2

公开(公告)日：2013-11-12

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US20130086545A1

公开(公告)日：2013-04-04

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US20130086544A1

公开(公告)日：2013-04-04

申请号：US13252067

申请日：2011-10-03

申请人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

摘要翻译： 通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。 针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。 在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。 引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。 优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。 阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

公开(公告)号：US08418113B1

公开(公告)日：2013-04-09

申请号：US13252067

申请日：2011-10-03

申请人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

摘要翻译： 通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。 针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。 在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。 引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。 优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。 阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

公开(公告)号：US20120124539A1

公开(公告)日：2012-05-17

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

公开(公告)号：US08667441B2

公开(公告)日：2014-03-04

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

公开(公告)号：US07761832B2

公开(公告)日：2010-07-20

申请号：US11941418

申请日：2007-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Tao Luo ,  David A. Papa ,  Chin Ngai Sze

发明人： Charles J. Alpert ,  Zhuo Li ,  Tao Luo ,  David A. Papa ,  Chin Ngai Sze

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a required arrival time (RAT) surface are generated for each net in the selected subcircuit. A slack pyramid for each net is generated from the difference between the RAT surface and delay pyramid of each net. The slack pyramids are grown and tested using test points to generate a worst-case slack region based on a plurality of slack pyramids in the selected subcircuit. The worst-case slack region is mapped on a placement region and a set of coordinates representing the optimal locations of the movable element(s) in the placement region are determined and outputted.

摘要翻译： 一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。 金字塔实用程序识别并选择可移动门以进行时序优化。 为所选择的子电路中的每个网络生成延迟金字塔和所需的到达时间（RAT）表面。 从每个网络的RAT表面和延迟金字塔之间的差异产生每个网络的松散金字塔。 使用测试点生长和测试松散的金字塔，以基于所选择的子电路中的多个松散金字塔产生最差情况的松弛区域。 最坏情况的松弛区域映射在放置区域上，并且确定并输出表示放置区域中的可移动元件的最佳位置的坐标系。

公开(公告)号：US20080288905A1

公开(公告)日：2008-11-20

申请号：US11748514

申请日：2007-05-15

申请人： Charles J. Alpert ,  Arvind K. Karandikar ,  Zhuo Li ,  Chin Ngai Sze

发明人： Charles J. Alpert ,  Arvind K. Karandikar ,  Zhuo Li ,  Chin Ngai Sze

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A computer implemented method, apparatus, and computer usable program product for modifying a circuit design are provided in the illustrative embodiments. A set of candidate areas within the circuit design is identified for making a change to the circuit design. A cost associated with each candidate area in the set of candidate areas is determined to form a set of costs. The cost associated with a candidate area is the cost of making the change to the circuit design in the candidate area. Using the set of costs, a candidate area is selected from the set of candidate areas in which to make the change to the circuit design.

摘要翻译： 在说明性实施例中提供了用于修改电路设计的计算机实现的方法，装置和计算机可用程序产品。 确定电路设计中的一组候选区域用于改变电路设计。 与候选区域集合中的每个候选区域相关联的成本被确定以形成一组成本。 与候选区域相关的成本是对候选区域中的电路设计进行更改的成本。 使用一组成本，从对电路设计进行改变的候选区域集合中选择候选区域。

公开(公告)号：US20120324409A1

公开(公告)日：2012-12-20

申请号：US13162806

申请日：2011-06-17

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

摘要翻译： 通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。 该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。 默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。 作为第二逻辑级中从输出门到第一门的线长度已知特性的函数调整默认转换速率。 基于输入转换速率来计算所选择的门的延迟。 输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

公开(公告)号：US08015532B2

公开(公告)日：2011-09-06

申请号：US11938824

申请日：2007-11-13

申请人： Charles J. Alpert ,  Zhuo Li ,  David A. Papa ,  Chin Ngai Sze

发明人： Charles J. Alpert ,  Zhuo Li ,  David A. Papa ,  Chin Ngai Sze

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks.

摘要翻译： 定时驱动的克隆方法将网络的宿迭代地分成不同的群集，并且对于每个集合来计算克隆的门位置的品质因数，其优化基于线性延迟的定时，即，与 克隆门位置和汇。 选择具有最高品质因数的集合作为最佳解决方案。 原始门也可以移动到定时优化的位置。 有利地使用由围绕原始门的金刚石区域定义的Voronoi多边形的边界来划分水槽，反之亦然。 品质因数可以是例如最差的松弛度，第二组中的汇的松弛度的总和，或者最差的松弛和松弛的总和的线性组合。