公开(公告)号：US20140029351A1

公开(公告)日：2014-01-30

申请号：US13557629

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang ,  Chen He ,  Richard K. Eguchi

发明人： Fuchen Mu ,  Yanzhuo Wang ,  Chen He ,  Richard K. Eguchi

IPC分类号： G11C16/06

CPC分类号： G11C29/021 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/028

摘要： Methods and systems are disclosed for adjusting program/erase bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and program/erase bias condition information within storage circuitry. The disclosed embodiments adjust program/erase bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations and interim verify based performance degradation determinations.

摘要翻译： 公开了用于调整非易失性存储器（NVM）单元的编程/擦除偏置条件以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以在存储电路内存储性能劣化信息和编程/擦除偏置条件信息。 所公开的实施例基于性能劣化确定来调整NVM单元的编程/擦除偏置条件，例如基于温度的性能劣化确定和基于临时验证的性能劣化确定。

公开(公告)号：US20140029350A1

公开(公告)日：2014-01-30

申请号：US13557449

申请日：2012-07-25

申请人： Fuchen Mu ,  Benjamin A. Schmid ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Benjamin A. Schmid ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/3495 ,  G11C7/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and systems are disclosed for adjusting read/verify bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having a NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and read/verify bias condition information within storage circuitry. The disclosed embodiments adjust read/verify bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations.

摘要翻译： 公开了用于调整非易失性存储器（NVM）单元的读取/验证偏置条件以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以在存储电路内存储性能劣化信息和读取/验证偏置条件信息。 所公开的实施例基于性能劣化确定（例如基于温度的性能降级确定）来调整NVM单元的读取/验证偏置条件。

公开(公告)号：US08363491B2

公开(公告)日：2013-01-29

申请号：US13016522

申请日：2011-01-28

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C7/00 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3459

摘要： In a system having a plurality of non-volatile memory cells, a method includes performing hot carrier injection on a first non-volatile memory cell in a first mode of programming. In the first mode, current flows from a first current electrode to a second electrode of the first non-volatile memory cell and charge is transferred from the current to a floating gate of the first non-volatile memory cell at a location nearer the first current electrode than the second current electrode. The method further includes performing hot carrier injection on the first non-volatile memory cell in a second mode of programming. In the second mode, current flows from the second current electrode to the first electrode of the first non-volatile memory cell and charge is transferred from the current to the floating gate of the first non-volatile memory cell at a location nearer the second current electrode than the first current electrode.

摘要翻译： 在具有多个非易失性存储单元的系统中，一种方法包括在第一编程模式下在第一非易失性存储单元上执行热载流子注入。 在第一模式中，电流从第一非易失性存储单元的第一电流流向第二电极，并且电荷从第一非易失性存储单元的电流转移到第一非易失性存储单元的接近第一电流的位置 电极比第二电流电极。 该方法还包括在第二编程模式中对第一非易失性存储器单元执行热载流子注入。 在第二模式中，电流从第一非易失性存储器单元的第二电流电极流向第一电极，并且电荷从第二非易失性存储单元的电流传送到第一非易失性存储单元的浮动栅极 电极比第一电流电极。

公开(公告)号：US08873316B2

公开(公告)日：2014-10-28

申请号：US13557481

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C7/00

CPC分类号： G11C16/12 ,  G11C29/021 ,  G11C29/028

摘要： Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements.

摘要翻译： 公开了用于对非易失性存储器（NVM）单元的偏置条件进行基于温度的调整以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以将基于温度的偏置条件信息存储在存储电路中。 所公开的实施例基于温度测量来选择和应用NVM单元的偏置条件。

公开(公告)号：US20140029335A1

公开(公告)日：2014-01-30

申请号：US13557481

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C29/021 ,  G11C29/028

摘要： Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements.

摘要翻译： 公开了用于对非易失性存储器（NVM）单元的偏置条件进行基于温度的调整以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以将基于温度的偏置条件信息存储在存储电路中。 所公开的实施例基于温度测量来选择和应用NVM单元的偏置条件。

公开(公告)号：US08947940B2

公开(公告)日：2015-02-03

申请号：US13361191

申请日：2012-01-30

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0483 ,  G11C16/349 ,  H01L21/28273

摘要： A semiconductor device comprises an array of memory cells. Each of the memory cells includes a tunnel dielectric, a well region including a first current electrode and a second current electrode, and a control gate. The first and second current electrodes are adjacent one side of the tunnel dielectric and the control gate is adjacent another side of the tunnel dielectric. A controller is coupled to the memory cells. The controller includes logic to determine when to perform a healing process in the tunnel dielectric of the memory cells, and to apply a first voltage to the first current electrode of the memory cells during the healing process to remove trapped electrons and holes from the tunnel dielectric.

摘要翻译： 半导体器件包括存储器单元的阵列。 每个存储单元包括隧道电介质，包括第一电流电极和第二电流电极的阱区以及控制栅极。 第一和第二电流电极邻近隧道电介质的一侧，并且控制栅极邻近隧道电介质的另一侧。 控制器耦合到存储器单元。 该控制器包括用于确定何时在存储器单元的隧道电介质中执行愈合过程的逻辑，并且在愈合过程期间向存储器单元的第一电流电极施加第一电压以从隧道电介质去除被俘获的电子和空穴 。

公开(公告)号：US08760923B2

公开(公告)日：2014-06-24

申请号：US13596764

申请日：2012-08-28

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： A semiconductor memory device comprises a memory controller, and an array of memory cells coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached. When the first charge trapping threshold has been reached, a second soft program operation is performed using second soft program voltages and a second soft program verify level.

摘要翻译： 半导体存储器件包括存储器控制器和耦合以与存储器控制器通信的存储器单元的阵列。 存储器控制器被配置为使用第一软编程电压和第一软程序验证电平来执行第一软编程操作，并且确定是否已经达到第一电荷捕获阈值。 当达到第一电荷捕获阈值时，使用第二软编程电压和第二软程序验证电平来执行第二软编程操作。

公开(公告)号：US09142315B2

公开(公告)日：2015-09-22

申请号：US13557449

申请日：2012-07-25

申请人： Fuchen Mu ,  Benjamin A. Schmid ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Benjamin A. Schmid ,  Yanzhuo Wang

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC分类号： G11C16/3495 ,  G11C7/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and systems are disclosed for adjusting read/verify bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having a NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and read/verify bias condition information within storage circuitry. The disclosed embodiments adjust read/verify bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations.

摘要翻译： 公开了用于调整非易失性存储器（NVM）单元的读取/验证偏置条件以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以在存储电路内存储性能劣化信息和读取/验证偏置条件信息。 所公开的实施例基于性能劣化确定（例如基于温度的性能降级确定）来调整NVM单元的读取/验证偏置条件。

公开(公告)号：US08879330B1

公开(公告)日：2014-11-04

申请号：US13874119

申请日：2013-04-30

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C11/34 ,  G11C16/34

CPC分类号： G11C16/3445 ,  G11C16/16

摘要： A method of erasing a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array. Erase pulses of the first number are applied to the NVM array. A first verify of the NVM is performed for a first time after commencing the applying after the first number has been reached.

摘要翻译： 擦除非易失性存储器（NVM）阵列的方法包括基于NVM阵列的温度确定第一数量。 将第一个数字的擦除脉冲施加到NVM阵列。 在达到第一个数字之后开始应用之后，首次执行NVM的第一次验证。

公开(公告)号：US20130308402A1

公开(公告)日：2013-11-21

申请号：US13476711

申请日：2012-05-21

申请人： Fuchen Mu ,  Paul A. Bogucki ,  Chen He

发明人： Fuchen Mu ,  Paul A. Bogucki ,  Chen He

IPC分类号： G11C29/04

CPC分类号： G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

摘要翻译： 用于检测非易失性存储器的泄漏位的技术包括擦除非易失性存储器的单元。 在擦除之后，对单元施加偏压应力。 在向单元施加偏置应力之后对单元执行擦除验证操作。 最后，基于各个单元的阈值电压是否低于擦除验证电平，确定单元是否通过或者失败擦除验证操作。