公开(公告)号：US20130194874A1

公开(公告)日：2013-08-01

申请号：US13755606

申请日：2013-01-31

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C16/3404 ,  G11C16/349

摘要： Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的动态愈合的方法和系统。 本文描述的动态愈合实施例在电荷（例如，空穴和/或电子）被俘获在这些隧道电介质层内的时间内，随着时间的推移而在NVM电池的隧道电介质层内松弛损伤。 关于可以应用哪些动态恢复过程的NVM操作包括例如擦除操作，程序操作和读取操作。 例如，在NVM系统的性能下降到NVM操作的选定性能水平之外，例如擦除/编程操作的擦除/编程脉冲计数升高以及读取操作的位错误，可以应用动态恢复。 可以应用各种愈合技术，例如排水应力过程，门应力过程和/或其他所需的愈合技术。

公开(公告)号：US09030883B2

公开(公告)日：2015-05-12

申请号：US13942814

申请日：2013-07-16

申请人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

发明人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C16/16

摘要： Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的自适应擦除恢复的方法和系统。 自适应擦除恢复实施例基于被擦除的NVM块的大小和操作温度自适应地调整擦除恢复放电速率和/或放电时间。 在一个示例性实施例中，通过调节在放电电路内使能的放电晶体管的数量来调整擦除恢复放电率，从而调节用于擦除恢复的放电电流。 查找表用于存储与要恢复的NVM块大小相关联的擦除恢复放电率和/或放电时间和/或工作温度。 通过自适应地控制擦除恢复放电率和/或时间，所公开的实施例提高了宽范围NVM块大小的整体擦除性能，同时避免了对NVM系统内的高电压电路的可能损坏。

公开(公告)号：US20150117112A1

公开(公告)日：2015-04-30

申请号：US14069195

申请日：2013-10-31

申请人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

发明人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C16/16 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

摘要翻译： 一种方法包括擦除其中块内的存储单元被同时擦除的多个存储单元块。 使用多次施加的擦除脉冲来执行多个块中的每个块的擦除。 擦除脉冲并行地施加到多个块。 在每次施加擦除脉冲之后执行擦除验证。 在擦除脉冲的数字应用之后，确定包括任何存储器单元组成的组之一的条件是否已经比第一预定量更多地被擦除，并且已经擦除了小于第二预定量的任何存储单元已被擦除 。 如果满足条件，则通过将擦除脉冲施加到具有独立于多个块的其他块的条件的具有存储器单元的块来继续擦除。

公开(公告)号：US20140029350A1

公开(公告)日：2014-01-30

申请号：US13557449

申请日：2012-07-25

申请人： Fuchen Mu ,  Benjamin A. Schmid ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Benjamin A. Schmid ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/3495 ,  G11C7/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3418

摘要： Methods and systems are disclosed for adjusting read/verify bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having a NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store performance degradation information and read/verify bias condition information within storage circuitry. The disclosed embodiments adjust read/verify bias conditions for the NVM cells based upon performance degradation determinations, for example, temperature-based performance degradation determinations.

摘要翻译： 公开了用于调整非易失性存储器（NVM）单元的读取/验证偏置条件以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以在存储电路内存储性能劣化信息和读取/验证偏置条件信息。 所公开的实施例基于性能劣化确定（例如基于温度的性能降级确定）来调整NVM单元的读取/验证偏置条件。

公开(公告)号：US08363491B2

公开(公告)日：2013-01-29

申请号：US13016522

申请日：2011-01-28

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C7/00 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3459

摘要： In a system having a plurality of non-volatile memory cells, a method includes performing hot carrier injection on a first non-volatile memory cell in a first mode of programming. In the first mode, current flows from a first current electrode to a second electrode of the first non-volatile memory cell and charge is transferred from the current to a floating gate of the first non-volatile memory cell at a location nearer the first current electrode than the second current electrode. The method further includes performing hot carrier injection on the first non-volatile memory cell in a second mode of programming. In the second mode, current flows from the second current electrode to the first electrode of the first non-volatile memory cell and charge is transferred from the current to the floating gate of the first non-volatile memory cell at a location nearer the second current electrode than the first current electrode.

摘要翻译： 在具有多个非易失性存储单元的系统中，一种方法包括在第一编程模式下在第一非易失性存储单元上执行热载流子注入。 在第一模式中，电流从第一非易失性存储单元的第一电流流向第二电极，并且电荷从第一非易失性存储单元的电流转移到第一非易失性存储单元的接近第一电流的位置 电极比第二电流电极。 该方法还包括在第二编程模式中对第一非易失性存储器单元执行热载流子注入。 在第二模式中，电流从第一非易失性存储器单元的第二电流电极流向第一电极，并且电荷从第二非易失性存储单元的电流传送到第一非易失性存储单元的浮动栅极 电极比第一电流电极。

公开(公告)号：US20150023106A1

公开(公告)日：2015-01-22

申请号：US13942814

申请日：2013-07-16

申请人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

发明人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C16/16

摘要： Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的自适应擦除恢复的方法和系统。 自适应擦除恢复实施例基于被擦除的NVM块的大小和操作温度自适应地调整擦除恢复放电速率和/或放电时间。 在一个示例性实施例中，通过调节在放电电路内使能的放电晶体管的数量来调整擦除恢复放电率，从而调节用于擦除恢复的放电电流。 查找表用于存储与要恢复的NVM块大小相关联的擦除恢复放电率和/或放电时间和/或工作温度。 通过自适应地控制擦除恢复放电率和/或时间，所公开的实施例提高了宽范围NVM块大小的整体擦除性能，同时避免了对NVM系统内的高电压电路的可能损坏。

公开(公告)号：US08873316B2

公开(公告)日：2014-10-28

申请号：US13557481

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C7/00

CPC分类号： G11C16/12 ,  G11C29/021 ,  G11C29/028

摘要： Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements.

摘要翻译： 公开了用于对非易失性存储器（NVM）单元的偏置条件进行基于温度的调整以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以将基于温度的偏置条件信息存储在存储电路中。 所公开的实施例基于温度测量来选择和应用NVM单元的偏置条件。

公开(公告)号：US20140029335A1

公开(公告)日：2014-01-30

申请号：US13557481

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C29/021 ,  G11C29/028

摘要： Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements.

摘要翻译： 公开了用于对非易失性存储器（NVM）单元的偏置条件进行基于温度的调整以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以将基于温度的偏置条件信息存储在存储电路中。 所公开的实施例基于温度测量来选择和应用NVM单元的偏置条件。

公开(公告)号：US09082493B2

公开(公告)日：2015-07-14

申请号：US14069195

申请日：2013-10-31

申请人： Chen He ,  Fuchen Mu ,  Yanzhuo Wang

发明人： Chen He ,  Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C11/34 ,  G11C16/16 ,  G11C16/34 ,  G11C16/14 ,  G11C11/56

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

摘要翻译： 一种方法包括擦除其中块内的存储单元被同时擦除的多个存储单元块。 使用多次施加的擦除脉冲来执行多个块中的每个块的擦除。 擦除脉冲并行地施加到多个块。 在每次施加擦除脉冲之后执行擦除验证。 在擦除脉冲的数字应用之后，确定包括任何存储器单元组成的组之一的条件是否已经比第一预定量更多地被擦除，并且已经擦除了小于第二预定量的任何存储单元已被擦除 。 如果满足条件，则通过将擦除脉冲施加到具有独立于多个块的其他块的条件的具有存储器单元的块来继续擦除。

公开(公告)号：US20150049555A1

公开(公告)日：2015-02-19

申请号：US13965731

申请日：2013-08-13

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/34 ,  G11C16/14

CPC分类号： G11C16/3459 ,  G11C16/14 ,  G11C16/345

摘要： Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

摘要翻译： 公开了用于NVM系统的嵌入式擦除操作期间用于非易失性存储器（NVM）单元的扩展擦除保护的方法和系统。 本文描述的实施例在嵌入式擦除操作中的软编程操作完成之后利用额外的阈值电压（Vt）检查，以提供NVM单元的扩展擦除保护。 特别地，NVM单元的阈值电压与阈值电压（Vt）检查电压（VCHK）电平进行比较，并且如果发现任何NVM单元超过阈值电压（Vt）检查电压（VCHK），执行附加的嵌入式擦除周期 ）级别。 阈值电压（Vt）检查电压（VCHK）电平可以是例如略高于擦除验证电压（VEV）电平并低于读取电压电平（VR）的电压电平。