公开(公告)号：US06728586B2

公开(公告)日：2004-04-27

申请号：US10047329

申请日：2002-01-14

申请人： Chao-Hsin Chang ,  Cheng-Hsi Wen ,  Edwin Liou

发明人： Chao-Hsin Chang ,  Cheng-Hsi Wen ,  Edwin Liou

IPC分类号： G06F1900

CPC分类号： G05B19/41865 ,  G05B2219/32085 ,  G05B2219/32117 ,  G05B2219/45031 ,  G06Q10/06 ,  G06Q10/0631 ,  G06Q50/04 ,  Y02P90/20 ,  Y02P90/24 ,  Y02P90/30

摘要： Within both a method for controlling microelectronic fabrication production and a system for controlling microelectronic fabrication production there is developed and evaluated for a plurality of microelectronic fabrication facilities a plurality of demand, allocation and output management plans prior to assigning and entering within at least one microelectronic fabrication facility a microelectronic fabrication order. The development and evaluation of the plurality of demand, allocation and output management plans provides for enhanced flexibility when assigning and entering the microelectronic fabrication order.

摘要翻译： 在用于控制微电子制造生产的方法和用于控制微电子制造生产的系统中，在分配和进入至少一个微电子制造之前，为多个微电子制造设备开发并评估了多个需求，分配和输出管理计划 设置微电子制造订单。 多个需求，分配和输出管理计划的开发和评估在分配和进入微电子制造订单时提供了增强的灵活性。

公开(公告)号：US6153497A

公开(公告)日：2000-11-28

申请号：US281335

申请日：1999-03-30

申请人： Renn-Shyan Yeh ,  Der-Fang Huang ,  Chao-Hsin Chang ,  Chih-Chien Hung

发明人： Renn-Shyan Yeh ,  Der-Fang Huang ,  Chao-Hsin Chang ,  Chih-Chien Hung

IPC分类号： G01N21/95 ,  H01L21/66 ,  H01L21/768 ,  H01L21/425

CPC分类号： H01L21/76801 ,  H01L22/24 ,  G01N21/9501 ,  H01L22/12

摘要： A method for determining a cause for defect formation in an insulating material layer deposited on an electrically conductive layer on a wafer surface is disclosed. In the method, on top of a semi-conducting wafer which has a first insulating material layer deposited, a second insulating material layer is deposited to replace an electrically conductive layer. A third insulating material layer is then deposited on top of the second insulating layer and a water jet which has a high pressure is scanned across a top surface of the third insulating layer with the wafer held in a stationary position. Surface defects are then counted in the predetermined path on the top surface of the third insulating layer for determining the cause for defect formation. When no defects are found, the formation is attributed to electrostatic discharges occurring in the metal conductive layer.

摘要翻译： 公开了一种用于确定沉积在晶片表面上的导电层上的绝缘材料层中形成缺陷的原因的方法。 在该方法中，在沉积有第一绝缘材料层的半导体晶片之上，沉积第二绝缘材料层以代替导电层。 然后将第三绝缘材料层沉积在第二绝缘层的顶部上，并且具有高压的水射流跨越第三绝缘层的顶表面扫描，晶片保持在静止位置。 然后在第三绝缘层的顶表面上的预定路径中计数表面缺陷，以确定缺陷形成的原因。 当没有发现缺陷时，形成归因于在金属导电层中发生的静电放电。

公开(公告)号：US6017771A

公开(公告)日：2000-01-25

申请号：US67264

申请日：1998-04-27

申请人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

发明人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.