公开(公告)号：US06727155B1

公开(公告)日：2004-04-27

申请号：US10323349

申请日：2002-12-18

申请人： Jiunn-Der Yang ,  Chaucer Chnug ,  Yuan-Chang Huang

发明人： Jiunn-Der Yang ,  Chaucer Chnug ,  Yuan-Chang Huang

IPC分类号： H01L21331

CPC分类号： H01L21/31116 ,  H01L29/6659

摘要： A method forming sidewall spacers on a semiconductor substrate without using the conventional plasma etching method is disclosed. In the method, a semiconductor substrate that has a gate structure formed on a top surface is first provided, followed by the deposition of a dielectric material layer on top of the semiconductor substrate. The substrate is then rotated to a rotational speed of at least 50 rpm, and an acid vapor is flown onto the substrate until the sidewall spacers are formed. The dielectric material layer for forming the sidewall spacers may be SiO2, SiON or Si3N4. The acid vapor utilized may be formed from an acid of HF, H3PO4, H2SO4 or HCl. In a preferred embodiment, the semiconductor substrate may be rotated to a rotational speed between about 100 rpm and about 150 rpm for a time period between about 10 sec. and about 20 sec.

摘要翻译： 公开了一种在不使用传统等离子体蚀刻方法的情况下在半导体衬底上形成侧壁间隔物的方法。 在该方法中，首先提供在顶表面上形成栅极结构的半导体衬底，随后在半导体衬底的顶部上沉积介电材料层。 然后将衬底旋转至至少50rpm的旋转速度，并将酸性蒸汽流到衬底上，直到形成侧壁间隔物。 用于形成侧壁间隔物的介电材料层可以是SiO 2，SiON或Si 3 N 4。 所使用的酸蒸汽可以由HF，H 3 PO 4，H 2 SO 4或HCl的酸形成。 在优选实施例中，半导体衬底可以旋转至约100rpm至约150rpm之间的旋转速度约10秒。 约20秒

公开(公告)号：US06211083B1

公开(公告)日：2001-04-03

申请号：US09550263

申请日：2000-04-17

申请人： Jiunn-Der Yang ,  Chaucer Chung ,  Yuan-Chang Huang

发明人： Jiunn-Der Yang ,  Chaucer Chung ,  Yuan-Chang Huang

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.

摘要翻译： 已经开发了在MOSFET器件的区域上形成低电阻二硅化钛层的工艺。 该方法的特征在于在第一相，高电阻，二硅化钛区域上沉积封盖的氧化硅层。 封装，氧化硅层具有压缩应力，降低了形成有拉伸应力的二硅化钛区域从MOSFET器件的下面区域的粘附损失或剥离的风险，例如从狭窄的顶部表面 宽度，多晶硅栅结构。 此外，封盖氧化硅层保护下游的二硅化钛区域与用于将第一相，高电阻，二硅化钛区域转化为第二相，低电阻，二硅化钛区域的退火循环期间使用的环境。

公开(公告)号：US6017771A

公开(公告)日：2000-01-25

申请号：US67264

申请日：1998-04-27

申请人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

发明人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

公开(公告)号：US06389323B1

公开(公告)日：2002-05-14

申请号：US09426405

申请日：1999-10-25

申请人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

发明人： Jiunn-Der Yang ,  Renn-Shyan Yeh ,  Chao-Hsin Chang ,  Wen-Chen Chang

IPC分类号： G06F1900

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

摘要翻译： 一种方法和系统提供用于确定在多个制造阶段制造半导体晶片的杀手级的屈服损失分析。 该方法包括以下步骤。 目视检查晶片上的半导体器件，以识别在晶片上制造的裸片上的视觉缺陷的位置，并通过位置维持模具上的视觉缺陷的计数。 检查晶片上的半导体管芯是否确定在每个制造阶段晶片上的缺陷管芯的位置和数量。 计算晶片每个阶段的有缺陷的裸片数量。 计算晶片每个阶段的有缺陷的坏死数。 确定有缺陷的坏死计数除以有缺陷的死亡计数的百分比。 绘制每个制造阶段产量损失百分比和有缺陷坏死率的百分比趋势。 比较图，从分析产量损失曲线与该阶段不良模具百分比的相对趋势分析确定杀手阶段。

公开(公告)号：US06373576B1

公开(公告)日：2002-04-16

申请号：US09459728

申请日：1999-12-13

申请人： Jiunn Der Yang

发明人： Jiunn Der Yang

IPC分类号： G01N2155

CPC分类号： H01L22/34 ,  G01N21/9501

摘要： A method for non-destructively testing for the concentration of a component of a film that is used for doping a region of a semiconductor wafer uses an image histogram of the light reflected from an array of points on the film and the underlying substrate. The image histogram has peaks that are characteristic of the composition of the film. Tests are run to establish the image histogram peaks for a film with a normal concentration of the components and for films with low and high concentrations. When the same test is made for the film of a production wafer, the concentration of the component is readily classified as normal, high, or low.

摘要翻译： 用于对用于掺杂半导体晶片的区域的膜的成分的浓度进行非破坏性测试的方法使用从膜上的点阵列和下面的基底反射的光的图像直方图。 图像直方图具有作为胶片组成的特征的峰。 进行测试以建立具有正常浓度组分的膜和具有低和高浓度的膜的图像直方图峰。 当对生产晶片的膜进行相同的测试时，组分的浓度容易分类为正常，高或低。