公开(公告)号：US06505274B2

公开(公告)日：2003-01-07

申请号：US09169402

申请日：1998-10-09

Applicant: Christian Tournier

Inventor： Christian Tournier

IPC: G06F1206

CPC classification number: G06F13/18

Abstract: Several peripheral entities are provided, with each peripheral entity being clocked by its own internal clock signal and being able to access a single-access memory. A priority entity is defined from among the peripheral entities, and the other peripheral entities are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows that are allocated to the peripheral entities. One of the peripheral entities is a microprocessor that is disabled for a fixed duration after each memory access request.

Abstract translation: 提供了几个外围实体，每个外围实体由其自己的内部时钟信号计时，并且能够访问单访问存储器。 优先实体从外围实体中定义，其他外围实体被定义为辅助实体。 制定重复时间框架，由优先实体的内部时钟信号进行调节，并将其细分为分配给外围实体的几组时间窗口。 外围实体之一是在每个存储器访问请求之后禁用固定持续时间的微处理器。

公开(公告)号：US06075382A

公开(公告)日：2000-06-13

申请号：US192022

申请日：1998-11-13

Applicant: Christian Tournier

Inventor： Christian Tournier

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K17/16 ,  H03K19/094

CPC classification number: H03K19/0013 ,  H03K19/00361

Abstract: The present invention relates to a buffer for logic signals including a MOS output transistor of a first conductivity type connected by its source to a first supply potential, the drain of this transistor forming an output terminal of the buffer; a control transistor for controlling the output transistor connected between the gate of the output transistor and a second supply potential; a third transistor of the first conductivity type connected between the gate of the output transistor and the first supply potential and controlled to maintain the gate-source voltage of the buffer close to a threshold voltage so that the output transistor operates as a current generator; and a fourth transistor connected to render floating the gate of the third transistor when the potential on the output terminal is close to the first supply potential.

Abstract translation: 本发明涉及一种用于逻辑信号的缓冲器，包括由其源极连接到第一电源电位的第一导电类型的MOS输出晶体管，该晶体管的漏极形成缓冲器的输出端; 控制晶体管，用于控制连接在输出晶体管的栅极和第二电源电位之间的输出晶体管; 第一导电类型的第三晶体管连接在输出晶体管的栅极和第一电源电位之间，并被控制以将缓冲器的栅极 - 源极电压保持接近阈值电压，使得输出晶体管作为电流发生器工作; 以及当输出端子上的电位接近第一电源电位时，第四晶体管连接成使第三晶体管的栅极浮置。

公开(公告)号：US5359650A

公开(公告)日：1994-10-25

申请号：US114292

申请日：1993-08-30

Applicant: Christian Tournier

Inventor： Christian Tournier

IPC: H04M19/08 ,  H04M3/00

CPC classification number: H04M19/08

Abstract: The invention relates to remotely powered circuitry, and in particular to telephones. The circuit of the invention uses a counter to measure or compare the duration of power supply interruptions on the remote power supplying line to cause the remotely powered circuitry to be initialized whenever the duration of such an interruption becomes greater than or less than a specified duration. Advantageously, comparators are used so as to be able to take a plurality of durations into consideration. Thus, each time the power supply on the remote power line is interrupted, if the interruption is not of an acceptable duration, then the remotely powered circuitry is initialized.

Abstract translation: 本发明涉及远程供电的电路，尤其涉及电话。 本发明的电路使用计数器来测量或比较远程供电线路上的电源中断的持续时间，以便在这种中断的持续时间大于或小于指定持续时间时，使远程供电的电路被初始化。 有利地，使用比较器以便能够考虑多个持续时间。 因此，每当远程电力线上的电源中断时，如果中断不是可接受的持续时间，则远程供电的电路被初始化。