公开(公告)号：US20080092096A1

公开(公告)日：2008-04-17

申请号：US11954626

申请日：2007-12-12

申请人： JASON BAUMGARTNER ,  Christian Jacobi ,  Viresh Paruthi ,  Kai Weber

发明人： JASON BAUMGARTNER ,  Christian Jacobi ,  Viresh Paruthi ,  Kai Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the design is selected for case-splitting. A first case-splitting is performed upon the selected node of the design to generate a primary constraint for setting the selected node to a primary value. A first constraining is performed on one of the one or more nodal binary decision diagrams with the primary constraint to generate a primary final binary decision diagram, a first verification of the design is performed using the primary final binary decision diagram.

摘要翻译： 提出了一种执行验证的方法。 该方法包括接收设计并构建用于包含一个或多个节点二进制决策图的设计的中间二进制决策图。 响应于超过尺寸阈值的中间二进制判定图的大小，设计的节点被选择用于案例分割。 在设计的所选节点上执行第一个案例分解，以生成将所选节点设置为主值的主约束。 在具有主要约束的一个或多个节点二进制决策图中的一个上执行第一约束以生成主要的最终二进制决策图，使用主要的最终二进制决策图来执行设计的第一次验证。

公开(公告)号：US07302656B2

公开(公告)日：2007-11-27

申请号：US11385928

申请日：2006-03-21

申请人： Kai Weber ,  Christian Jacobi ,  Nico Gulden ,  Viresh Paruthi ,  Klaus Keuerleber

发明人： Kai Weber ,  Christian Jacobi ,  Nico Gulden ,  Viresh Paruthi ,  Klaus Keuerleber

IPC分类号： G06F9/45

CPC分类号： G06F17/504

摘要： A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced (51) by pseudo inputs. The input signal values of the multiplier circuit are determined (54) automatically from a counterexample (53) delivered (52) by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined (55) with other known inputs to form a test case (56) file that can be used by a logic simulator to analyse the counterexample (52) on the unmodified hardware design including the multiplier.

摘要翻译： 一种用于执行功能验证逻辑电路的方法，计算机程序产品和系统。 本发明通过更换不能被正式验证的部件容易地实现对硬件逻辑设计的功能形式验证。 在一种形式中，本发明应用于包括乘法器电路的逻辑设计。 乘法器被伪输入替换（51）。 乘法器电路的输入信号值通过功能形式验证系统自动地从通过伪信号代替乘法器的修改设计的函数形式验证系统（52）自动地从反例（53）中确定（54）。 输入信号值与其他已知输入组合（55）以形成测试用例（56）文件，该文件可被逻辑模拟器用于在包括乘数的未修改的硬件设计上分析反例（52）。

公开(公告)号：US20070061765A1

公开(公告)日：2007-03-15

申请号：US11225651

申请日：2005-09-13

申请人： Christian Jacobi ,  Geert Janssen ,  Viresh Paruthi ,  Kai Weber

发明人： Christian Jacobi ,  Geert Janssen ,  Viresh Paruthi ,  Kai Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.

摘要翻译： 用于执行验证的方法包括：为设计接收设计和构建包含表示一个或多个变量的一个或多个节点的中间二进制判定图集。 通过将第一个胖子变量设置为一个初始值，对由一个或多个节点表示的一个或多个变量中的第一个胖子变量执行第一个分解，并且对该中间二进制判定图集执行第一个共同构想 相对于使用主值的逆的一个或多个节点来生成第一辅因子二进制决策图集。 对相对于一个或多个节点设置的中间二进制判定图，使用主值来生成第二共有二元决策图集，执行第二共同构想，并且通过评估第二构成二进制的属性来执行设计的验证 决策图集。

公开(公告)号：US20060294481A1

公开(公告)日：2006-12-28

申请号：US11165455

申请日：2005-06-23

申请人： Jason Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Kai Weber

发明人： Jason Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Kai Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the design is selected for case-splitting. A first case-splitting is performed upon the selected node of the design to generate a primary constraint for setting the selected node to a primary value. A first constraining is performed on one of the one or more nodal binary decision diagrams with the primary constraint to generate a primary final binary decision diagram, a first verification of the design is performed using the primary final binary decision diagram.

摘要翻译： 提出了一种执行验证的方法。 该方法包括接收设计并构建用于包含一个或多个节点二进制决策图的设计的中间二进制决策图。 响应于超过尺寸阈值的中间二进制判定图的大小，设计的节点被选择用于案例分割。 在设计的所选节点上执行第一个案例分解，以生成将所选节点设置为主值的主约束。 在具有主要约束的一个或多个节点二进制决策图中的一个上执行第一约束以生成主要的最终二进制决策图，使用主要的最终二进制决策图来执行设计的第一次验证。

公开(公告)号：US20060190868A1

公开(公告)日：2006-08-24

申请号：US11050592

申请日：2005-02-03

申请人： Jason Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Kai Weber

发明人： Jason Baumgartner ,  Christian Jacobi ,  Viresh Paruthi ,  Kai Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more nodes of the design. A binary decision diagram for the initial state function of one or more state variables of the design is generated and the design is subsequently initialized. Binary decisions diagrams for one or more constraints are synthesized. A set of constraint values is accumulated over time by combining the binary decision diagrams for the one or more constraints with a set of previously generated binary decision diagrams for a set of constraints previously used in one or more previous time-steps. A binary decision diagram for the next state function of the one or more state variables in the design is constructed in the presence of the constraints. The one or more state variables in the design are updated by propagating the binary decision diagram for the next state function to the one or more state variables and a set of binary decision diagrams for the one or more targets in the presence of the one or more constraints is calculated. The set of binary decision diagrams for one or more targets is constrained and the design is verified by determining whether the one or more targets were hit.

摘要翻译： 公开了一种通过符号仿真验证设计的方法。 该方法包括为包含一个或多个状态变量的设计中的一个或多个输入创建一个或多个二进制决策图变量，以及为设计的一个或多个节点的第一节点构建二进制决策图。 生成设计的一个或多个状态变量的初始状态函数的二进制决策图，随后初始化设计。 合成一个或多个约束的二进制决策图。 通过将一个或多个约束的二进制判定图与先前在一个或多个先前时间步骤中使用的一组约束的先前生成的二进制决策图的组合来累积一组约束值。 设计中一个或多个状态变量的下一个状态函数的二进制决策图是在有约束的情况下构建的。 设计中的一个或多个状态变量通过将下一个状态函数的二进制决策图传播到一个或多个状态变量和一个或多个目标的存在下的一个或多个目标的一组二进制决策图来更新 计算约束。 用于一个或多个目标的二进制决策图集被约束，并且通过确定一个或多个目标是否被击中来验证设计。

公开(公告)号：US20060047680A1

公开(公告)日：2006-03-02

申请号：US10926587

申请日：2004-08-26

申请人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Weber

发明人： Viresh Paruthi ,  Christian Jacobi ,  Geert Janssen ,  Jiazhao Xu ,  Kai Weber

IPC分类号： G06F7/00

CPC分类号： G06F17/30958 ,  G06F17/504 ,  Y10S707/99942

摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.

摘要翻译： 公开了一种用于使用动态资源约束和交错深度优先搜索和修改的宽度优先搜索时间表在数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。 该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。 然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定 使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。 响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。 响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。

公开(公告)号：US20130096901A1

公开(公告)日：2013-04-18

申请号：US13271472

申请日：2011-10-12

申请人： Wolfgang Gellerich ,  Guenter Mayer ,  Chung-Lung K. Shum ,  Kai Weber

发明人： Wolfgang Gellerich ,  Guenter Mayer ,  Chung-Lung K. Shum ,  Kai Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/504

摘要： A mechanism is provided for verifying design modifications to a simulation design unit included within a simulation model of an integrated electronic device. A modified description is received of a simulation design unit that failed to meet an expected physical property value during an initial simulation of the entire integrated electronic device. A simulation of the simulation design unit is executed using a list of identified input signals from a trace file. The trace file is generated during the initial simulation and indicates state values for the list of identified input signals. A determination is made as to whether the simulation of the simulation design unit fails to meet the expected physical property value. An indication is generated that modifications made to an initial description of the simulation design unit are successful in response to the simulation of the simulation design unit meeting the expected physical property value.

摘要翻译： 提供了用于验证对包括在集成电子设备的仿真模型内的模拟设计单元的设计修改的机制。 接收到在整个集成电子设备的初始模拟期间不能满足预期物理属性值的模拟设计单元的修改的描述。 使用来自跟踪文件的已识别输入信号的列表来执行仿真设计单元的模拟。 跟踪文件在初始仿真期间生成，并指示已识别输入信号列表的状态值。 确定模拟设计单元的仿真是否不能满足预期的物理属性值。 产生对模拟设计单元的初始描述进行的修改成功响应于满足预期物理属性值的模拟设计单元的模拟的指示。

公开(公告)号：US20120258809A1

公开(公告)日：2012-10-11

申请号：US13440048

申请日：2012-04-05

申请人： Kai Weber

发明人： Kai Weber

IPC分类号： B21H3/02 ,  C22C9/04 ,  C22F1/08 ,  C22C9/10 ,  B22D11/00 ,  B22D17/00 ,  C22C9/02 ,  C22C9/01

CPC分类号： C22C9/02 ,  F16C33/121 ,  F16C2204/12

摘要： The invention relates to a copper-tin multicomponent bronze consisting of (in % by weight): 0.5 to 14.0% Sn, 0.01 to 8.0% Zn, 0.01 to 0.8% Cr, 0.05 to 2.0% Al, 0.01 to 2.0% Si, optionally in addition up to a maximum of 0.1 to 3.0% Mn and optionally in addition up to a maximum of 0.08% P and optionally in addition up to a maximum of 0.08% S, remainder copper and unavoidable impurities, wherein, in the structure, silicides and/or chromium particles are deposited, which are surrounded by a tin film in the form of a highly tin-containing accumulation. A further aspect of the invention relates to a process for producing strips, plates, bolts, wires, rods, tubes and profiles of the copper-tin multicomponent bronze according to the invention, and also to a use.

摘要翻译： 本发明涉及一种由（重量百分比）：（重量％）：0.5〜14.0％Sn，0.01〜8.0％Zn，0.01〜0.8％Cr，0.05〜2.0％Al，0.01〜2.0％Si， 另外最多可达到0.1至3.0％的Mn，另外最多可达0.08％P，另外最多可达0.08％S，余下为铜和不可避免的杂质，其中，在该结构中，硅化物 和/或铬颗粒沉积，其被含有高含锡堆积形式的锡膜包围。 本发明的另一方面涉及根据本发明的用于生产铜锡多组分青铜的条，板，螺栓，线，棒，管和轮廓的方法，并且还涉及一种用途。

公开(公告)号：US08249848B2

公开(公告)日：2012-08-21

申请号：US12182211

申请日：2008-07-30

申请人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

发明人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

IPC分类号： G06F17/50

CPC分类号： G06F9/3859 ,  G06F17/5022 ,  G06F2217/68

摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

摘要翻译： 公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。 该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中维护的信息包括完全执行的执行长度的确定 指令，将关于完全执行的指令的维护信息与由用户通过陷阱文件提供的一组陷阱元素相匹配，并且响应于在维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中 和至少一个捕获元件。

公开(公告)号：US20090022620A1

公开(公告)日：2009-01-22

申请号：US12215191

申请日：2008-06-25

申请人： Kai Weber

发明人： Kai Weber

IPC分类号： C22C9/04 ,  C22F1/08 ,  B21C37/06

CPC分类号： C22C9/04 ,  C22F1/08 ,  F16C33/121 ,  F16C2204/10

摘要： The invention relates to a copper-zinc alloy, consisting of (in wt %): from 28.0 to 36.0% Zn, from 0.5 to 2.3% Si, from 1.5 to 2.5% Mn, from 0.2 to 3.0% Ni, from 0.5 to 1.5% Al, from 0.1 to 1.0% Fe, optionally also up to at most 0.1% Pb, optionally also up to at most 0.2% Sn, optionally also up, to at most 0.1% P, optionally also up to 0.08% S, remainder Cu and inevitable impurities, with mixed silicides of iron-nickel-manganese incorporated in the matrix.

摘要翻译： 本发明涉及一种铜锌合金，由（重量％）：由28.0至36.0％的Zn，0.5至2.3％的Si，1.5至2.5％的Mn，0.2至3.0％的Ni，0.5至1.5 ％Al，0.1至1.0％的Fe，任选还至多至0.1％的Pb，任选还最多至0.2％的Sn，任选地还可以至多至0.1％的P，任选地还至多0.08％的S，余量 Cu和不可避免的杂质，掺入铁 - 镍 - 锰的混合硅化物。