公开(公告)号：US20190259402A1

公开(公告)日：2019-08-22

申请号：US16170524

申请日：2018-10-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Masoud FARSHBAF ZINATI ,  Arun RAMANI ,  Amar VELLANKI ,  Xiaofan FEI

IPC: G10L19/032 ,  H03F3/183 ,  H03F3/217 ,  G10L19/008 ,  G10L19/26

Abstract: A method may include receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit, detecting an invalid state associated with the stream, and responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.

公开(公告)号：US20190253031A1

公开(公告)日：2019-08-15

申请号：US16140663

申请日：2018-09-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Amar VELLANKI ,  Tejasvi DAS ,  John L. MELANSON

IPC: H03G3/30 ,  H03F3/217

CPC classification number: H03G3/3031 ,  H03F3/217

Abstract: A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.

公开(公告)号：US20190115886A1

公开(公告)日：2019-04-18

申请号：US16133045

申请日：2018-09-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Alan Mark MORTON ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI ,  Johann G. GABORIAU ,  John L. MELANSON ,  Amar VELLANKI

IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00

Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.