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公开(公告)号：US20190260365A1
公开(公告)日：2019-08-22
申请号：US16144104
申请日：2018-09-27
Inventor： Ku HE , Tejasvi DAS , Xin ZHAO , Xiaofan FEI
Abstract: A method may include, in a system comprising a digital PWM subsystem having a tunable digital gain, a first path coupled to an output of the digital PWM subsystem and configured to drive an open-loop driver stage, and a second path coupled to the output of the digital PWM subsystem and configured to drive a closed-loop driver stage having a tunable analog gain: selecting one of the first path and the second path for processing an input signal to generate an output signal based on one or more characteristics of the input signal, setting the digital gain to a maximum digital gain and the analog gain to a minimum analog gain when the input signal is lesser than a first threshold, setting the digital gain to a minimum digital gain and the analog gain to a maximum analog gain when the input signal is greater than a second threshold magnitude, and varying the analog gain and the digital gain when the input signal is in a range greater than the first threshold and lesser than a second threshold.
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公开(公告)号：US20200343871A1
公开(公告)日：2020-10-29
申请号：US16928444
申请日：2020-07-14
Inventor： Johann G. GABORIAU , David M. OLIVENBAUM , Xiaofan FEI , Amar VELLANKI , Venugopal CHOUKINISHI , Gautham SIVASANKAR , Wai-Shun SHUM
Abstract: A method for calibrating gain in a multi-path subsystem having a first processing path, a second processing path, and a mixed signal return path, may include low-pass filtering an input signal and a mixed signal return path signal generated from the input signal at subsonic frequencies to generate a filtered input signal and a filtered mixed signal return path signal and tracking and correcting for a gain difference between the first processing path and the second processing path based on the filtered input signal and the filtered mixed signal return path signal.
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公开(公告)号：US20180091102A1
公开(公告)日：2018-03-29
申请号：US15277465
申请日：2016-09-27
Inventor： Xin ZHAO , Tejasvi DAS , Xiaofan FEI , Alan Mark MORTON
CPC classification number: H03F3/2171 , H03F1/32 , H03F1/342 , H03F3/181 , H03F3/187 , H03F3/217 , H03F3/2173 , H03F3/38 , H03F3/72 , H03F2200/345 , H03F2200/351
Abstract: An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.
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4.发明公开公开(公告)号：US20230379592A1
公开(公告)日：2023-11-23
申请号：US18318896
申请日：2023-05-17
Inventor： Wai-Shun SHUM , Amar VELLANKI , Jeffrey SKARZYNSKI , Gautham S. SIVASANKAR , Xingdong DAI , Venugopal CHOUKINISHI , Xiaofan FEI , Xin ZHAO
IPC: H04N23/90
CPC classification number: H04N23/90
Abstract: A system for relaying communication for a PHY/data link level communication protocol may include a first device having a first and second transceiver, the first transceiver having a first protocol controller configured to detect a first bus condition and second transceiver having a second protocol controller configured to detect a second bus condition and a switching matrix coupled to the first and second transceiver and configured to operate in a relaying mode to enable: the first protocol controller to control a physical layer of the second transceiver and enables the second protocol controller to control a physical layer of the first transceiver, a physical layer of a first transmitter of the first transceiver to receive an output of a second receiver of the second transceiver, and the physical layer of a second transmitter of the second transceiver to receive an output of a first receiver of the first transceiver.
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公开(公告)号：US20190115909A1
公开(公告)日：2019-04-18
申请号：US16219187
申请日：2018-12-13
Inventor： Tejasvi DAS , Alan Mark MORTON , Xin ZHAO , Lei ZHU , Xiaofan FEI , Johann G. GABORIAU , John L. MELANSON , Amar VELLANKI
CPC classification number: H03K7/08 , G06F1/025 , H02M3/157 , H02M2001/0012 , H03F3/183 , H03F3/2175
Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.
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Patent Agency Ranking
公开(公告)号：US20180295442A1
公开(公告)日：2018-10-11
申请号：US15482250
申请日：2017-04-07
Inventor： Tejasvi DAS , Xin ZHAO , Ku HE , Xiaofan FEI
CPC classification number: H04R3/00 , H03F1/0277 , H03F3/185 , H03F3/211 , H03F3/217 , H03F3/2178 , H03F3/30 , H03F3/72 , H03F2200/03 , H03F2200/411 , H03F2200/432 , H04R29/00 , H04R2420/03
Abstract: In accordance with embodiments of the present disclosure, a system may include a playback path and a control circuit. The playback path may have a playback input for receiving an input signal and configured to generate at a playback path output an output signal based on the input signal, wherein the playback path is configured to operate in a plurality of operational modes. The control circuit may be configured to receive a first signal from within the playback path and indicative of the input signal, receive a second signal generated from the input signal externally to the playback path, and select a selected operational mode from the plurality of operational modes based on the first signal and the second signal.
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公开(公告)号：US20210175896A1
公开(公告)日：2021-06-10
申请号：US16945520
申请日：2020-07-31
Inventor： John L. MELANSON , Johann G. GABORIAU , Lei ZHU , Wai-Shun SHUM , Xiaofan FEI , Leyi YIN
Abstract: A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.
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公开(公告)号：US20210175895A1
公开(公告)日：2021-06-10
申请号：US16945288
申请日：2020-07-31
Inventor： John L. MELANSON , Johann G. GABORIAU , Lei ZHU , Wai-Shun SHUM , Xiaofan FEI , Leyi YIN
Abstract: A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.
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9.发明申请公开(公告)号：US20200044616A1
公开(公告)日：2020-02-06
申请号：US16190427
申请日：2018-11-14
Inventor： Tejasvi DAS , Eric J. KING , Xin ZHAO , Xiaofan FEI , Johann G. GABORIAU , Lei ZHU , John L. MELANSON , Thomas HOFF
Abstract: A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.
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公开(公告)号：US20180159488A1
公开(公告)日：2018-06-07
申请号：US15884912
申请日：2018-01-31
Inventor： Xin ZHAO , Tejasvi DAS , Xiaofan FEI , Alan Mark MORTON
CPC classification number: H03F3/2171 , H03F1/32 , H03F1/342 , H03F3/181 , H03F3/187 , H03F3/217 , H03F3/2173 , H03F3/38 , H03F3/72 , H03F2200/345 , H03F2200/351
Abstract: An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.
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