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11.发明授权Integrated circuit, method of manufacturing an integrated circuit, and memory module 有权集成电路，集成电路的制造方法和存储器模块公开(公告)号：US07855435B2
公开(公告)日：2010-12-21
申请号：US12047167
申请日：2008-03-12
IPC分类号： H01L23/48
CPC分类号： H01L43/08 , G11C11/15 , G11C11/1675
摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.
摘要翻译： 根据本发明的一个实施例，提供了包括多个存储单元的集成电路。 每个存储单元包括电阻率变化存储元件，其包括设置在顶部电极和底部电极之间的顶部电极，底部电极和电阻率变化材料。 每个电阻率变化记忆元件至少部分地被绝热结构包围。 热绝缘结构被布置成使得在电阻率变化的存储元件内产生的热量消耗到电阻率变化存储元件的环境中降低。
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公开(公告)号：US20090085121A1
公开(公告)日：2009-04-02
申请号：US11864575
申请日：2007-09-28
申请人： Human Park , Ulrich Klostermann , Rainer Leuschner
发明人： Human Park , Ulrich Klostermann , Rainer Leuschner
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/228 , H01L27/2436 , H01L29/66795 , H01L29/785
摘要： An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
摘要翻译： 对集成电路的集成电路及其制造方法进行说明。 在一个实施例中，集成电路包括包括电阻率变化存储元件的存储单元。 电阻率变化存储元件电耦合到选择晶体管，该选择晶体管包括在源极和漏极之间形成在衬底表面上方的源极，漏极和鳍状结构的FinFET。 翅片结构包括在基本上平行于衬底的表面的方向上延伸的沟道区，以及围绕沟道区的至少一部分形成的介电层，使得选择晶体管的有效沟道宽度至少部分依赖于 翅片结构的高度。
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13.发明申请Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module 有权集成电路，制造集成电路的方法和存储器模块公开(公告)号：US20090230379A1
公开(公告)日：2009-09-17
申请号：US12047167
申请日：2008-03-12
IPC分类号： H01L45/00 , H01L21/762
CPC分类号： H01L43/08 , G11C11/15 , G11C11/1675
摘要： According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered.
摘要翻译： 根据本发明的一个实施例，提供了包括多个存储单元的集成电路。 每个存储单元包括电阻率变化存储元件，其包括设置在顶部电极和底部电极之间的顶部电极，底部电极和电阻率变化材料。 每个电阻率变化记忆元件至少部分地被绝热结构包围。 热绝缘结构被布置成使得在电阻率变化的存储元件内产生的热量消耗到电阻率变化存储元件的环境中降低。
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公开(公告)号：US20070069296A1
公开(公告)日：2007-03-29
申请号：US11369194
申请日：2006-03-06
IPC分类号： H01L27/12
CPC分类号： H01L27/228 , B82Y10/00
摘要： A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size to be decreased without decreasing the current that is driven by the transistor. According to the invention, this is achieved by increasing the length of gate portions of one or more transistors within the active area of a cell to increase the effective transistor width. In one embodiment, two transistors, electrically connected in parallel, are used per cell. The two transistors double the effective transistor width within the cell relative to a single transistor design. Such cell designs can be used with a variety of devices, including various types of MRAM and PCRAM.
摘要翻译： 描述了通过将电池中的晶体管的有效宽度增加到大于电池的有效面积的实际宽度来减小大电流器件（例如MRAM）中的电池单元尺寸的电池设计和方法。 这允许在不降低由晶体管驱动的电流的情况下降低电池尺寸。 根据本发明，这通过增加单元的有效区域内的一个或多个晶体管的栅极部分的长度来增加有效晶体管宽度来实现。 在一个实施例中，每个单元使用并联电连接的两个晶体管。 两个晶体管相对于单晶体管设计，使单元内的有效晶体管宽度倍增。 这样的单元设计可以与各种设备一起使用，包括各种类型的MRAM和PCRAM。
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15.发明申请MRAM Device Structure Employing Thermally-Assisted Write Operations and Thermally-Unassisted Self-Referencing Operations 有权采用热辅助写入操作和热辅助自我参考操作的MRAM器件结构公开(公告)号：US20100002501A1
公开(公告)日：2010-01-07
申请号：US12168671
申请日：2008-07-07
CPC分类号： G11C7/04 , B82Y25/00 , B82Y40/00 , G11C11/16 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01F41/307 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.
摘要翻译： 提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。 抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。 人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。 阻挡层被定位在第二磁性层和自由磁性层之间。
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16.发明申请Integrated Circuits; Methods for Manufacturing an Integrating Circuit; Memory Modules 审中-公开集成电路; 集成电路制造方法; 内存模块公开(公告)号：US20090073737A1
公开(公告)日：2009-03-19
申请号：US11856659
申请日：2007-09-17
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08
摘要： Embodiments of the invention relate generally to integrated circuits, to methods for manufacturing an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit is provided having a memory cell. The memory cell may include a first magnetic layer structure, a tunnel barrier layer structure disposed above the first magnetic layer structure, a second magnetic layer structure disposed above the tunnel barrier layer structure, and at least one sacrificial material layer to suppress electrochemical corrosion of the first magnetic layer structure or the second magnetic layer structure.
摘要翻译： 本发明的实施例一般涉及集成电路，用于制造集成电路的方法以及存储器模块。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括第一磁性层结构，设置在第一磁性层结构之上的隧道阻挡层结构，设置在隧道势垒层结构之上的第二磁性层结构，以及至少一个牺牲材料层，以抑制 第一磁性层结构或第二磁性层结构。
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17.发明授权MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations 有权采用热辅助写入操作和热辅助自参考操作的MRAM器件结构公开(公告)号：US08310866B2
公开(公告)日：2012-11-13
申请号：US12168671
申请日：2008-07-07
CPC分类号： G11C7/04 , B82Y25/00 , B82Y40/00 , G11C11/16 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01F41/307 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.
摘要翻译： 提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。 抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。 人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。 阻挡层被定位在第二磁性层和自由磁性层之间。
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18.发明授权Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit 有权集成电路，存储单元阵列，存储器模块和操作集成电路的方法公开(公告)号：US07903454B2
公开(公告)日：2011-03-08
申请号：US12114466
申请日：2008-05-02
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
摘要翻译： 根据本发明的一个实施例，集成电路包括多个热可选择存储单元，每个存储单元连接到导电线，该导线具有用于施加加热电流的第一部分和用于施加加热电流的第二部分 编程电流。 集成电路被配置为使得加热电流和编程电流可以彼此独立地分别路由到导线的第一和第二部分。
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19.发明授权Adiabatic rotational switching memory element including a ferromagnetic decoupling layer 失效绝热旋转开关存储元件，包括铁磁去耦层公开(公告)号：US07205596B2
公开(公告)日：2007-04-17
申请号：US11117713
申请日：2005-04-29
申请人： Ulrich Klostermann , Peter Beer , Manfred Ruehrig
发明人： Ulrich Klostermann , Peter Beer , Manfred Ruehrig
IPC分类号： H01L29/76
CPC分类号： H01L43/08 , H01F10/30 , H01F10/3254 , H01F10/3272 , H01F10/3295
摘要： A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region including a free magnetization that is free to be switched between oppositely aligned directions with respect to an easy axis thereof; and a tunneling barrier made of a non-magnetic material. The ferromagnetic reference and free regions and the tunneling barrier together form a magnetoresistive tunneling junction. The ferromagnetic free region includes a plurality of N ferromagnetic free layers being magnetically coupled such that magnetizations of adjacent ferromagnetic free layers are in antiparallel alignment, where N is an integer greater than or equal to two. The ferromagnetic free region further includes at least one ferromagnetic decoupling layer including frustrated magnetization in orthogonal alignment to ferromagnetic free layer magnetizations and being arranged in between adjacent ferromagnetic free layers.
摘要翻译： 磁阻存储元件包括具有包括固定磁化强度的铁磁参考区的堆叠结构; 铁磁自由区域，包括相对于其容易轴线在相对排列的方向之间自由切换的自由磁化; 以及由非磁性材料制成的隧道屏障。 铁磁参考和自由区和隧道势垒一起形成磁阻隧道结。 铁磁自由区包括磁耦合的多个N个铁磁自由层，使得相邻铁磁自由层的磁化反平行对准，其中N是大于或等于2的整数。 铁磁自由区还包括至少一个铁磁解耦层，其包括与铁磁自由层磁化正交对准的失效磁化，并布置在相邻的铁磁自由层之间。
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20.发明申请Adiabatic rotational switching memory element including a ferromagnetic decoupling layer 失效绝热旋转开关存储元件，包括铁磁去耦层公开(公告)号：US20060244021A1
公开(公告)日：2006-11-02
申请号：US11117713
申请日：2005-04-29
申请人： Ulrich Klostermann , Peter Beer , Manfred Ruehrig
发明人： Ulrich Klostermann , Peter Beer , Manfred Ruehrig
IPC分类号： H01L29/94
CPC分类号： H01L43/08 , H01F10/30 , H01F10/3254 , H01F10/3272 , H01F10/3295
摘要： A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region including a free magnetization that is free to be switched between oppositely aligned directions with respect to an easy axis thereof; and a tunneling barrier made of a non-magnetic material. The ferromagnetic reference and free regions and the tunneling barrier together form a magnetoresistive tunneling junction. The ferromagnetic free region includes a plurality of N ferromagnetic free layers being magnetically coupled such that magnetizations of adjacent ferromagnetic free layers are in antiparallel alignment, where N is an integer greater than or equal to two. The ferromagnetic free region further includes at least one ferromagnetic decoupling layer including frustrated magnetization in orthogonal alignment to ferromagnetic free layer magnetizations and being arranged in between adjacent ferromagnetic free layers.
摘要翻译： 磁阻存储元件包括具有包括固定磁化强度的铁磁参考区的堆叠结构; 铁磁自由区域，包括相对于其容易轴线在相对排列的方向之间自由切换的自由磁化; 以及由非磁性材料制成的隧道屏障。 铁磁参考和自由区和隧道势垒一起形成磁阻隧道结。 铁磁自由区包括磁耦合的多个N个铁磁自由层，使得相邻铁磁自由层的磁化反平行对准，其中N是大于或等于2的整数。 铁磁自由区还包括至少一个铁磁解耦层，其包括与铁磁自由层磁化正交对准的失效磁化，并布置在相邻的铁磁自由层之间。
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