公开(公告)号：US06636511B1

公开(公告)日：2003-10-21

申请号：US09717472

申请日：2000-11-21

Applicant: Subhash C. Roy ,  Michael M. Renault ,  Frederick R. Carter ,  David K. Toebes ,  Rajen S. Ramchandani ,  Daniel C. Upp

Inventor： Subhash C. Roy ,  Michael M. Renault ,  Frederick R. Carter ,  David K. Toebes ,  Rajen S. Ramchandani ,  Daniel C. Upp

IPC: H04L1228

CPC classification number: H04L12/6402 ,  H04L2012/6413

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

Abstract translation: 网络交换机包括至少一个端口处理器和至少一个开关元件。 端口处理器具有SONET OC-x接口（用于TDM流量），UTOPIA接口（用于ATM和数据包流量）以及与交换机元件的接口。 在一个实施例中，端口处理器具有等同于OC-48的总I / O带宽，并且交换单元具有12×12端口，总带宽为30Gbps。 典型的交换机包括多个端口处理器和交换机元件。 使用9行×1700个时隙的数据帧将ATM，TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。 每帧在125微秒内传输; 每行在13.89微秒。 每个插槽包括一个4位标签加上一个4字节的有效载荷。 时隙带宽为2.592Mbps，足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针，当指定TDM连接时，该指针将被设置。 帧的最后20个时隙被保留用于链路开销。 因此，该帧能够承载1,680个E-1 TDM信号的等效物。 对于ATM和分组数据，为64字节的有效载荷定义了16个时隙的PDU（协议数据单元）。 PDU通过具有28位路由标签的交换机进行自路由，该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。 在保持TDM定时的同时，在ATM和分组连接之间仲裁带宽。

公开(公告)号：US6104724A

公开(公告)日：2000-08-15

申请号：US961932

申请日：1997-10-29

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: H04J3/16

CPC classification number: H04L12/403

Abstract: An asynchronous data transfer and source traffic control system includes a bus master and a plurality of bus users coupled to a bidirectional data bus. The bus master provides two clock signals to each bus user, a system clock and a frame clock. The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users may request access which is received by the bus master. During the grant field, the bus master grants access to a selected bus user for the entire data portion of the next frame. Which user is granted access to the next frame is determined according to an arbitration algorithm in the bus master which may be unknown to the bus users. The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.

Abstract translation: 异步数据传输和源流量控制系统包括总线主机和耦合到双向数据总线的多个总线用户。 总线主机为每个总线用户提供两个时钟信号，一个系统时钟和一个帧时钟。 帧时钟指定帧的开始。 帧格式优选地包括十五或十六个系统时钟周期，其中第一个被指定为请求字段，其中最后一个包括授权字段。 一个或多个其它周期可被分配控制和/或路由信息，并且其余周期包括固定长度的数据字段。 在请求字段期间，任何数量的总线用户可以请求由总线主机接收的访问。 在授权字段期间，总线主机授权对所选总线用户访问下一帧的整个数据部分。 根据总线主机中可能对总线用户不了解的仲裁算法确定哪个用户被授权访问下一个帧。 异步数据传输和源流量控制系统在适应BISDN系统中使用的ATM信元的内容传输方面具有特殊的应用。

公开(公告)号：US5033064A

公开(公告)日：1991-07-16

申请号：US439097

申请日：1989-11-17

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: G06F5/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/16 ,  H04L7/02

CPC classification number: H04J3/1611 ,  G06F5/06 ,  H04J3/076 ,  G06F2205/061 ,  G06F2205/123

Abstract: A DS1 dejitter circuit has a control circuit for generating six pulses over a one hundred and ninety three 1.544 Mb/sec clock cycle, and a clock circuit for tracking the frequency of a jittered incoming DS1 signal, and based on that frequency, and utilizing the six pulses, generating a clean DS1 signal at the nominal rate of the jittered incoming signal. The control circuit preferably includes a divide by 28 or 29 circuit which receives a 44.736 Mb/sec (DS3) input clock signal, a mod 193 counter, and a count decoder for providing the six control pulses over the 193 count. Logic circuitry is provided for taking the outputs from the count decode and controlling the divide block to guarantee that the divide block divides the DS3 signal by 29 one hundred eighty-eight times for every five times the divide block divides the DS3 signal by 28. In this manner an average clock of 1.544 Mb/sec (the standard DS1) rate is obtained from the divide block. The clock circuit includes a FIFO, a clock rate control circuit and another divide by 28 or 29 block. The FIFO receives the incoming jittered DS1 signal. The clock rate control circuit senses how full the FIFO is, and using that information along with the pulses from the control circuit regulates the divide block to divide the DS3 signal by 28 either four, five, or six times in a one hundred ninety-three clock cycle. Where it is desired to dejitter a plurality of DS1 signals, a single common control circuit can be used to supply the six control pulses to a plurality of clock rate control circuits.

Abstract translation: DS1去抖电路具有用于在一百九十三个1.544Mb / sec时钟周期内产生六个脉冲的控制电路，以及用于跟踪抖动的进入DS1信号的频率的时钟电路，并且基于该频率，并利用 六个脉冲，以惊人的进入信号的标称速率产生干净的DS1信号。 控制电路优选地包括28或29电路的除法，其接收44.736Mb / sec（DS3）输入时钟信号，mod 193计数器和用于在193个计数上提供六个控制脉冲的计数解码器。 提供逻辑电路用于从计数解码和控制除法块的输出中获取输出，以保证划分块将DS3信号每隔五分之一除以二十八八倍，除法将DS3信号除以28。 以这种方式，从分割块获得平均时钟为1.544Mb / sec（标准DS1）速率。 时钟电路包括一个FIFO，一个时钟速率控制电路，另一个除以28或29块。 FIFO接收传入的抖动DS1信号。 时钟速率控制电路检测FIFO的充满程度，并且使用该信息以及来自控制电路的脉冲来调节除法块，以在第一百九十三个中将DS3信号除以28或4或5或6次 时钟周期。 在需要去除多个DS1信号的情况下，可以使用单个公共控制电路来将六个控制脉冲提供给多个时钟速率控制电路。

公开(公告)号：US4608684A

公开(公告)日：1986-08-26

申请号：US593342

申请日：1984-03-26

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: H04Q11/04

CPC classification number: H04Q11/04 ,  H05B2214/04

Abstract: There is disclosed an apparatus for enabling one to increase the bandwidth of a multi-channel digital switching system. Essentially, the system allows one to set up multi-channel link paths to obtain a total band width of N times the bandwidth of a typical switching path in a digital switching network. To do this, a common frame counter is located in the unused bit positions of the sample in each of the paths, forming a wideband channel. At the receive end, the apparatus de-skews the received samples to properly reassembly the output. This operation is provided by utilizing one content addressable memory and an associated random access memory (CAM/RAM) (C/R) for each channel to be joined. The width of each C/R is twelve bits, eight for data, the read-out section and four for frame counter, which is the associative section. The length of each C/R is a function of the maximum skew to be counted. A four bit output frame counter provides the associative addresses for the C/R which, when given an associative address corresponding to a frame number, will respond with an eight bit data word for that frame or with an Empty signal, meaning that no word exists for that frame number. At initialization the frame counter presets to one and all C/Rs are interrogated to see if they contain frame one information. If they do not, then the output frame counter is indexed and all C/Rs are re-interrogated at a fast rate until they all indicate not Empty. At this point, the outputs of each C/R for the frame count indicated are assembled into an output word. Thus as long as all the C/Rs indicate not Empty, frame integrity is insured, and hence the distributed control switching system can provide wideband operation via multi-channel linked paths while insuring frame integrity.

Abstract translation: 公开了一种能够增加多信道数字交换系统的带宽的装置。 本质上，该系统允许建立多信道链路路径以获得数字交换网络中典型交换路径带宽的N倍的总带宽。 为此，公共帧计数器位于每个路径中的样本的未使用位位置，形成宽带信道。 在接收端，设备使收到的样本偏移，以正确重新组合输出。 该操作通过利用一个内容可寻址存储器和相关联的随机存取存储器（CAM / RAM）（C / R）来提供，用于要连接的每个通道。 每个C / R的宽度为十二位，数据为八位，读出区为四位，为相关区段。 每个C / R的长度是要计数的最大倾斜度的函数。 四位输出帧计数器提供用于C / R的相关地址，当给定对应于帧号的关联地址时，将用该帧或空信号的八位数据字进行响应，这意味着没有字存在 对于该帧号。 在初始化时，帧计数器预设为一个和所有C / Rs被询问以查看它们是否包含帧一信息。 如果没有，则输出帧计数器被索引并且所有C / Rs都以快速的速率被重新询问，直到它们都表示不为空。 此时，指示的帧计数的每个C / R的输出被组合成输出字。 因此，只要所有的C / Rs表示不为空，则保证帧完整性，因此分布式控制交换系统可以通过多信道链路提供宽带操作，同时确保帧完整性。

公开(公告)号：US4293946A

公开(公告)日：1981-10-06

申请号：US96599

申请日：1979-11-21

Applicant: Michael L. Kuras ,  Daniel C. Upp ,  Herbert J. Toegel

Inventor： Michael L. Kuras ,  Daniel C. Upp ,  Herbert J. Toegel

IPC: H04M3/56 ,  H04Q11/04

CPC classification number: H04M3/561 ,  H04Q11/04 ,  H04M2203/205

Abstract: A system is disclosed which permits information received from any data terminal or telephone subscriber line at any interface to a digital network to be transmitted to any number of other terminals at any or all of the interfaces to the digital network. The system herein described also permits any terminal at any interface of the digital network to be conferenced, with up to N other terminals at any or all of the interfaces to the digital network where N can be made to depend solely upon the topology and single path transmission delay of the digital network itself. A facility is provided which is independently provisioned at every interface to the digital network and which is independently and concurrently available to any number of combinations of terminals and simplex paths at those interfaces. A broadcast capability is also provided whereby telecommunication information can be simultaneously transmitted from a source terminal to a plurality of destination terminals.

Abstract translation: 公开了一种系统，其允许在与数字网络的任何接口处的数字网络的任何接口处从任何数据终端或电话用户线路接收到的信息被发送到任何或所有到数字网络的接口的任何数量的其他终端。 本文描述的系统还允许在数字网络的任何接口处的任何终端与数字网络的任何或所有接口中的多达N个其他终端进行会议，其中N可以仅依赖于拓扑和单个路径 数字网络本身的传输延迟。 提供了在每个接口处独立地提供给数字网络的设施，并且在这些接口处独立地并且可用于任何数量的终端和单工路径的组合。 还提供广播能力，由此电信信息可以从源终端同时发送到多个目的地终端。

公开(公告)号：US06636515B1

公开(公告)日：2003-10-21

申请号：US09717999

申请日：2000-11-21

Applicant: Subhash C. Roy ,  Santanu Das ,  Daniel C. Upp ,  William B. Lipp ,  Jitender K. Vij ,  Michael M. Renault ,  Frederick R. Carter ,  Rajen S. Ramchandani

Inventor： Subhash C. Roy ,  Santanu Das ,  Daniel C. Upp ,  William B. Lipp ,  Jitender K. Vij ,  Michael M. Renault ,  Frederick R. Carter ,  Rajen S. Ramchandani

IPC: H04L1228

CPC classification number: H04L12/6402 ,  H04L2012/6413

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

Abstract translation: 网络交换机包括至少一个端口处理器和至少一个开关元件。 端口处理器具有SONET OC-x接口（用于TDM流量），UTOPIA接口（用于ATM和数据包流量）以及与交换机元件的接口。 在一个实施例中，端口处理器具有等同于OC-48的总I / O带宽，并且交换单元具有12×12端口，总带宽为30Gbps。 典型的交换机包括多个端口处理器和交换机元件。 使用9行×1700个时隙的数据帧将ATM，TDM和分组数据从端口处理器通过一个或多个交换元件传输到相同或另一个端口处理器。 每帧在125微秒内传输; 每行在13.89微秒。 每个插槽包括一个4位标签加上一个4字节的有效载荷。 时隙带宽为2.592Mbps，足够大以承载具有开销的E-1信号。 4位标签是交叉连接指针，当指定TDM连接时，该指针将被设置。 帧的最后20个时隙被保留用于链路开销。 因此，该帧能够承载1,680个E-1 TDM信号的等效物。 对于ATM和分组数据，为64字节的有效载荷定义了16个时隙的PDU（协议数据单元）。 PDU通过具有28位路由标签的交换机进行自路由，该路由标签允许通过每个阶段使用4位的七个交换阶段进行路由。 在保持TDM定时的同时，在ATM和分组连接之间仲裁带宽。

公开(公告)号：US06577651B2

公开(公告)日：2003-06-10

申请号：US09768430

申请日：2001-01-24

Applicant: Kumar Shakti Singh ,  Pawan Goyal ,  Arnab Basak ,  Vikas Kumar ,  Daniel C. Upp

Inventor： Kumar Shakti Singh ,  Pawan Goyal ,  Arnab Basak ,  Vikas Kumar ,  Daniel C. Upp

IPC: H04J306

CPC classification number: H04J3/076 ,  H04J3/0623

Abstract: Methods for retiming and realigning SONET signals include demultiplexing STS-1 signals from an STS-3 signal, buffering each of the three signals in a FIFO, determining the FIFO depth over time, determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. For a 28-byte deep FIFO, if the depth of a FIFO is 12-16 bytes, no pointer leaking is performed. If the depth is 0-4 bytes, an immediate positive leak is performed. If the depth is 24-28, an immediate negative leak is performed. If the depth is 5-11 bytes a calculated positive leak is performed. If the depth is 17-23 bytes, a calculated negative leak is performed. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received every 32 seconds (256,000 frames).

公开(公告)号：US5548534A

公开(公告)日：1996-08-20

申请号：US272259

申请日：1994-07-08

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: G06F5/10 ,  G06F5/12 ,  H04J3/07 ,  H04J3/06

CPC classification number: G06F5/12 ,  H04J3/076 ,  G06F2205/061 ,  G06F2205/126

Abstract: A two stage desynchronizer is provided to receive a gapped data component of an STS-3C (STM-1) signal and provide therefrom an ungapped DS-4NA (E4) data signal. The first stage includes a data byte formation block which takes the gapped STS-3C payload data and formulates the data into bytes, a first FIFO which receives the bytes, and a first FIFO read controller which utilizes the STS-3C clock signal and causes bytes of data to be read out according to a schedule which reads bytes eight or nine times out of every ten STS-3C clock cycles. For each row (270 byte times) of the STS-3C frame, either 241 or 242 bytes are read out of the FIFO according to a slightly gapped schedule where the reading of the 242nd byte at least partially depends upon the number of stuffs in the signal and the pointer movements received. The second stage of the desynchronizer includes a second FIFO, a FIFO fullness measurement block, and a VCXO. The FIFO fullness measurement block uses the incoming slightly gapped byte clock and the ungapped DS-4NA output clock as inputs for effectively measuring the relative fullness of the second FIFO, and provides a control signal based on the relative fullness. The control signal is fed to the voltage controlled crystal oscillator (VCXO) which generates the ungapped DS-4NA or E4 clock in response thereto.

Abstract translation: 提供两级去同步器以接收STS-3C（STM-1）信号的间隙数据分量，从而提供无间隙DS-4NA（E4）数据信号。 第一级包括数据字节形成块，其获取有间隙的STS-3C有效载荷数据并将数据形成字节，接收字节的第一FIFO，以及利用STS-3C时钟信号并产生字节的第一FIFO读控制器 根据每十个STS-3C时钟周期读取字节八或九次的调度读出的数据。 对于STS-3C帧的每一行（270字节时间），根据稍微有间隙的时间表，从FIFO读出241或242字节，其中第242个字节的读取至少部分地取决于 信号和指针移动接收。 去同步器的第二级包括第二FIFO，FIFO饱和度测量块和VCXO。 FIFO饱和度测量块使用传入的稍微有间隙的字节时钟和无间隙的DS-4NA输出时钟作为有效测量第二个FIFO的相对丰满度的输入，并且基于相对丰满度提供控制信号。 控制信号被馈送到电压控制晶体振荡器（VCXO），该晶体振荡器响应于此产生无间隙DS-4NA或E4时钟。

公开(公告)号：US5297180A

公开(公告)日：1994-03-22

申请号：US805465

申请日：1991-12-10

Applicant: Daniel C. Upp ,  Dan H. Wolaver

Inventor： Daniel C. Upp ,  Dan H. Wolaver

IPC: G06F5/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/16 ,  H04L7/02 ,  H04L7/00

CPC classification number: G06F5/06 ,  H04J3/076 ,  H04J3/1611 ,  G06F2205/061 ,  G06F2205/123

Abstract: A digital clock dejitter circuit has a RAM for receiving an incoming gapped signal, a digital, fractional RAM fullness gauge for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge has write and read counters which track the movement of data into and out of the RAM, and a subtractor for taking the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator has an adder, a register, and a fast clock counter (FCC) which provides the fullness gauge with a fractional digital indication of the RAM depth. The adder has a carry output fed to the FCC to control whether the FCC divides by x or x+1, and a remainder output fed to the register and then fed back as an input to the adder. The adder also receives the control indication from the fullness gauge as an input. FCC inputs include the fast clock, and the carry output of the adder. The FCC outputs are a read signal for causing a byte to be read from the RAM at the end of a count cycle, and the fast clock count used for fractional fullness.

Abstract translation: 数字时钟去抖电路具有用于接收输入间隙信号的RAM，用于跟踪来自RAM和从其产生控制指示的平均输入和输出速率的数字分数RAM饱和度计，以及可控数字频率发生器， 接收快速时钟信号和控制指示，并且向其提供与入射间隙信号相同的额定速率下的基本上无抖动的时钟信号。 RAM充满度计具有写入和读取计数器，其跟踪数据进出RAM的移动，以及减法器，用于获取计数器的差异以获得RAM深度的整数值。 可控数字频率发生器具有加法器，寄存器和快速时钟计数器（FCC），其向饱和度计提供RAM深度的分数字数字指示。 加法器具有馈送到FCC的进位输出，用于控制FCC是否将x除x或x + 1，剩余输出馈送到寄存器，然后作为输入反馈给加法器。 加法器还从饱和度计作为输入接收控制指示。 FCC输入包括快速时钟和加法器的进位输出。 FCC输出是一个读取信号，用于在计数周期结束时从RAM读取一个字节，并且快速时钟计数用于分数饱和。

公开(公告)号：US5289507A

公开(公告)日：1994-02-22

申请号：US857928

申请日：1992-05-13

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: G06F5/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/16 ,  H04L7/02 ,  H04L7/00 ,  H04J3/06

CPC classification number: H04J3/1611 ,  G06F5/06 ,  H04J3/076 ,  G06F2205/061 ,  G06F2205/123

Abstract: Clock dejitter circuits are provided and comprise control circuits for generating a plurality of pulses over a clock cycle, and clock circuits for tracking the speeds of jittered incoming data signal and based on those speeds, and utilizing the plurality of pulses generating substantially unjittered data signals at the nominal rates of the jittered incoming signals. A control circuit broadly includes a divide by value x-divide by value x+1 circuit which receives a fast input clock signal, a modulus y counter, and a count decode for providing z control pulses over the count of y, and a logic gate for taking the outputs from the count decode and controlling the divide block to guarantee hat the divide block divides the fast input clock signal by value x q times for every r times the divide block divides the fast input clock signal by value x+1; wherein q plus r equals y, and z equals either q+1 or r+1.

Abstract translation: 提供时钟分离电路并且包括用于在时钟周期上产生多个脉冲的控制电路，以及用于跟踪抖动的输入数据信号的速度并基于那些速度的时钟电路，以及利用产生基本上未抖动的数据信号的多个脉冲 惊人的进入信号的标称速率。 控制电路广泛地包括接收快速输入时钟信号的值x + 1电路除数x分频，模y计数器和用于在y的计数上提供z控制脉冲的计数解码，以及逻辑门 为了从计数解码和控制分割块获取输出，以确保除法器块将快速输入时钟信号除以每x r次的xq倍，除法将快速输入时钟信号除以值x + 1; 其中q加r等于y，z等于q + 1或r + 1。