公开(公告)号：US5911051A

公开(公告)日：1999-06-08

申请号：US721686

申请日：1996-09-27

申请人： David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case ,  Kim A. Meinerth ,  Brian K. Langendorf

发明人： David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case ,  Kim A. Meinerth ,  Brian K. Langendorf

IPC分类号： G06F13/16 ,  G06F13/14

CPC分类号： G06F13/1631 ,  G06F13/161 ,  G06F13/1615

摘要： A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.

摘要翻译： 提供了高吞吐量的存储器访问接口。 该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该接口允许以这样的方式执行存储器访问请求，使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。 每个访问请求包括命令位，地址位和长度位。 在发起设备中，每个访问请求被分成三个段，它们存储在起始设备和目标设备中的单独的寄存器中。 目标设备只需要包含最低位地址位和长度位的段来启动总线事务。 因此，如果其他两个段中的任何一个从先前的访问请求起没有改变，则这样的段或段不被发送到目标。 如果这些片段或片段自从先前的访问请求以来已经改变，那么它们被提供给目标，仅用于更新目标中的状态。 访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。

公开(公告)号：US5555420A

公开(公告)日：1996-09-10

申请号：US175776

申请日：1993-12-30

申请人： Nitin V. Sarangdhar ,  P. K. Nizar ,  David G. Carson

发明人： Nitin V. Sarangdhar ,  P. K. Nizar ,  David G. Carson

IPC分类号： G06F13/26 ,  G06F15/17 ,  G06F9/46

CPC分类号： G06F15/17 ,  G06F13/26

摘要： A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done via the system bus. IAU acceptance logic is minimized by allowing retry of a delivered message when the acceptance latches are full. The increase in interrupt bus traffic due to retry is minimized by controlling the time intervals between rebroadcasts of unaccepted IRQs. Exponential timers control this interval so that each succeeding interval is a multiplicative factor, typically 2, greater than the preceding interval.

摘要翻译： 多处理器可编程中断控制器系统具有与系统（存储器）总线不同的中断总线，用于处理与中断请求（IRQ）相关的消息。 每个处理器芯片具有耦合到中断总线的板载中断接受单元（IAU），以接收IRQ并广播其产生的IRQ。 I / O设备中断线连接到一个或多个中断传送单元（IDU），每个中断传送单元都连接到中断总线以广播I / O生成的IRQ。 中断总线是一个同步三线总线，具有一个时钟线和两条数据传输线。 用于由IAU和IDU控制中断总线的仲裁使用数据线之一。 最低优先级IRQ传递模式使用类似的单线仲裁程序来确定哪个IAU具有在其相关的片上处理器中运行的最低当前优先级任务。 对此程序的修改还可以将IRQ统一分配给符合条件的处理器。 IRQ的实际服务通过系统总线完成。 当接收锁存器已满时，允许重传所传送的消息，IAU接受逻辑被最小化。 通过控制不接受的IRQ的重播之间的时间间隔，可以最大限度地减少因重试引起的中断总线流量的增加。 指数定时器控制此间隔，以便每个后续间隔是乘法因子，通常为2，大于前一个间隔。