公开(公告)号：US5555420A

公开(公告)日：1996-09-10

申请号：US175776

申请日：1993-12-30

申请人： Nitin V. Sarangdhar ,  P. K. Nizar ,  David G. Carson

发明人： Nitin V. Sarangdhar ,  P. K. Nizar ,  David G. Carson

IPC分类号： G06F13/26 ,  G06F15/17 ,  G06F9/46

CPC分类号： G06F15/17 ,  G06F13/26

摘要： A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done via the system bus. IAU acceptance logic is minimized by allowing retry of a delivered message when the acceptance latches are full. The increase in interrupt bus traffic due to retry is minimized by controlling the time intervals between rebroadcasts of unaccepted IRQs. Exponential timers control this interval so that each succeeding interval is a multiplicative factor, typically 2, greater than the preceding interval.

摘要翻译： 多处理器可编程中断控制器系统具有与系统（存储器）总线不同的中断总线，用于处理与中断请求（IRQ）相关的消息。 每个处理器芯片具有耦合到中断总线的板载中断接受单元（IAU），以接收IRQ并广播其产生的IRQ。 I / O设备中断线连接到一个或多个中断传送单元（IDU），每个中断传送单元都连接到中断总线以广播I / O生成的IRQ。 中断总线是一个同步三线总线，具有一个时钟线和两条数据传输线。 用于由IAU和IDU控制中断总线的仲裁使用数据线之一。 最低优先级IRQ传递模式使用类似的单线仲裁程序来确定哪个IAU具有在其相关的片上处理器中运行的最低当前优先级任务。 对此程序的修改还可以将IRQ统一分配给符合条件的处理器。 IRQ的实际服务通过系统总线完成。 当接收锁存器已满时，允许重传所传送的消息，IAU接受逻辑被最小化。 通过控制不接受的IRQ的重播之间的时间间隔，可以最大限度地减少因重试引起的中断总线流量的增加。 指数定时器控制此间隔，以便每个后续间隔是乘法因子，通常为2，大于前一个间隔。

公开(公告)号：US5410710A

公开(公告)日：1995-04-25

申请号：US176136

申请日：1993-12-30

申请人： Nitin V. Sarangdhar ,  Dave Papworth ,  P. K. Nizar ,  David G. Carson

发明人： Nitin V. Sarangdhar ,  Dave Papworth ,  P. K. Nizar ,  David G. Carson

IPC分类号： G06F13/26 ,  G06F15/17 ,  G06F13/18

CPC分类号： G06F13/26 ,  G06F15/17

摘要： A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a subharmonic of the FRC unit master CPU clock, for handling interrupt request (IRQ) related messages and maintaining synchronism between the master and checker CPUs of the FRC unit. Additional embodiments provide for the use of D-type flip-flop synchronizers to accommodate FRC units whose internal (core) clock or external bus clock are not harmonically related to the interrupt clock frequency. Each processor unit has an interrupt acceptance unit (IAU) coupled to the interrupt bus for the acceptance of IRQs and for broadcasting of IRQs generated by its associated on-chip processor. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two data wires for 2-bit parallel-serial data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to the lowest priority mode arbitration procedure also provides for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus.

摘要翻译： 一种用于多处理器系统的多处理器可编程中断控制器系统，其中一个处理器单元是功能冗余校验（FRC）单元，具有与系统（存储器）总线不同的同步中断总线，具有中断总线时钟 频率是FRC单元主CPU时钟的次谐波，用于处理中断请求（IRQ）相关消息，并保持FRC单元的主站和检查CPU之间的同步。 另外的实施例提供使用D型触发器同步器来容纳其内部（核心）时钟或外部总线时钟与中断时钟频率没有谐波相关性的FRC单元。 每个处理器单元具有耦合到中断总线的中断接受单元（IAU），用于接收IRQ和用于广播由其相关联的片上处理器产生的IRQ。 I / O设备中断线连接到一个或多个中断传送单元（IDU），每个中断传送单元都连接到中断总线，用于广播I / O生成的IRQ。 中断总线是一个同步三线总线，具有一个时钟线和两个数据线用于2位并行 - 串行数据传输。 用于由IAU和IDU控制中断总线的仲裁使用数据线之一。 最低优先级IRQ传递模式使用类似的单线仲裁程序来确定哪个IAU具有在其相关的片上处理器中运行的最低当前优先级任务。 对最优先权模式仲裁程序的修改还规定了IRQ向符合条件的处理器的均匀分配。 IRQ的实际服务是通过系统总线完成的。

公开(公告)号：US5495615A

公开(公告)日：1996-02-27

申请号：US176122

申请日：1993-12-30

申请人： P. K. Nizar ,  David G. Carson ,  Adi Golbert ,  David Finzi ,  Yoav Hochberg

发明人： P. K. Nizar ,  David G. Carson ,  Adi Golbert ,  David Finzi ,  Yoav Hochberg

IPC分类号： G06F13/26 ,  G06F15/17

CPC分类号： G06F15/17 ,  G06F13/26

摘要： A multiprocessor programmable interrupt controller (MPIC) system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt-related messages. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated interrupt request messages. Each processor chip has an on-board interrupt acceptance unit (IAU) that can accept interrupt requests from the interrupt bus and can broadcast on the interrupt bus interrupt request messages generated by its associated processor. Each processor can request to read the contents of the IAU control registers that are associated with another target processor. In that case, a remote read request message is generated by the IAU of the local processor and responded to, without software intervention, by the IAU of the target processor. A remote read status field indicates to the local processor the status of the data contained in a remote read register. The remote IAU is expected to respond in a fixed number of interrupt bus cycles. If the remote agent is unable to do so, then the remote read status field becomes "Invalid." If successful, the remote read status resolves to "Valid." The processor polls this field to determine the completion and success of the remote read request. Remote read requests are always successful (although the data may be valid or invalid) in that they are never retried. Remote read requests are primarily a debug feature, and a "hung" remote IAU that is unable to respond to a remote read request should not cause the debugging software to hang on the local processor.

摘要翻译： 多处理器可编程中断控制器（MPIC）系统具有与系统（存储器）总线不同的中断总线，用于处理与中断有关的消息。 I / O设备中断线连接到一个或多个中断传送单元（IDU），每个中断传送单元都连接到中断总线，用于广播I / O生成的中断请求消息。 每个处理器芯片都有一个板载中断接受单元（IAU），可以接受来自中断总线的中断请求，并可以在中断总线上广播由其关联的处理器生成的中断请求消息。 每个处理器可以请求读取与另一个目标处理器相关联的IAU控制寄存器的内容。 在这种情况下，远程读取请求消息由本地处理器的IAU生成，并且由目标处理器的IAU在没有软件干预的情况下进行响应。 远程读取状态字段向本地处理器指示包含在远程读取寄存器中的数据的状态。 远程IAU预计将以固定数量的中断总线周期进行响应。 如果远程代理不能这样做，则远程读取状态字段变为“无效”。 如果成功，则远程读取状态解析为“有效”。 处理器轮询此字段以确定远程读取请求的完成和成功。 远程读取请求始终是成功的（尽管数据可能是有效的或无效的），因为它们不会被重试。 远程读取请求主要是调试功能，无法响应远程读取请求的“挂起”远程IAU不应导致调试软件挂起在本地处理器上。

公开(公告)号：US4473880A

公开(公告)日：1984-09-25

申请号：US342837

申请日：1982-01-26

申请人： David L. Budde ,  David G. Carson ,  Stephen R. Colley ,  David B. Johnson ,  Robert P. Voll ,  Doran K. Wilde

发明人： David L. Budde ,  David G. Carson ,  Stephen R. Colley ,  David B. Johnson ,  Robert P. Voll ,  Doran K. Wilde

IPC分类号： G06F13/374 ,  G06F3/00 ,  H04J6/00

CPC分类号： G06F13/374

摘要： An arbitration mechanism comprising a request FIFO (408) for storing ones and zeros corresponding to received requests in the order that they are made. A one indicates that the request was made by the module in which the FIFO is located, and a zero indicates that the request was made by one of a number of other similar modules. The request status information from the other modules is received over signal lines (411) connected between the modules. This logic separates multiple requests into time-ordered slots, such that all requests in a particular time slot may be serviced before any requests in the next time slot. A store (409) stores a unique logical module number. An arbiter (410) examines this logical number bit-by-bit in successive cycles and places a one in a grant queue (412) upon the condition that the bit examined in a particular cycle is a zero and signals this condition over the signal lines. If the bit examined in a particular cycle is a one, the arbiter drops out of contention and signals this condition over the signal lines (411). This logic orders multiple requests within a single time slot, which requests are made by multiple modules, in accordance with the logical module numbers of the modules making the requests. The grant queue (412) stores status information (ones and zeros) corresponding to granted requests in the order that they are granted--a one indicating that the granted request was granted to the module in which the grant queue is located, and a zero indicating that the granted request was granted to one of the other modules. The granted request status information from the other modules is received over the signal lines (411). This logic separates multiple granted requests such that only one request corresponding to a particular module is at the head of any one grant queue at any one time.

摘要翻译： 一种仲裁机制，包括：请求FIFO（408），用于按照它们的顺序存储对应于接收的请求的1和0。 一个表示该请求是由FIFO所在的模块进行的，零表示该请求由多个其他类似的模块之一进行。 来自其他模块的请求状态信息通过连接在模块之间的信号线（411）来接收。 该逻辑将多个请求分离成时间有序的时隙，使得特定时隙中的所有请求可以在下一个时隙中的任何请求之前被服务。 存储（409）存储唯一的逻辑模块号。 仲裁器（410）在连续循环中逐位检查该逻辑数字，并且在特定周期中检查的位为零并且在信号线上发出信号的条件下将一个放在授权队列（412）中 。 如果在特定周期中检查的比特是一个，则仲裁者退出争用，并通过信号线（411）发信号通知该条件。 该逻辑根据发出请求的模块的逻辑模块编号，在单个时隙内订购多个请求，该请求由多个模块进行。 授权队列（412）按照被许可的顺序存储对应于被许可的请求的状态信息（一个和零） - 一个指示授予的请求被授予给予授权队列所在的模块的状态信息，一个零表示 授予的请求被授予其他模块之一。 通过信号线（411）接收来自其他模块的授权请求状态信息。 该逻辑分离多个授权请求，使得只有一个对应于特定模块的请求在任何一个时间处于任何一个授权队列的头部。

公开(公告)号：US4503535A

公开(公告)日：1985-03-05

申请号：US393906

申请日：1982-06-30

申请人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

发明人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/2002 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/0781 ,  G06F11/0784 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1637 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/2028

摘要： A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an error recurs the node at which the error exists initiates an error message which is received and repropagated on the error report lines by all nodes. The error message identifies the type of error and the node ID at which the error was detected. Confinement area isolation logic in a node isolates a faulty confinement area of which the node is a part, upon the condition that the node ID in an error report message identifies the node as a node which is a part of a faulty confinement area. Logic in the node reconfigures at least part of the system upon the condition that the node ID in the error report message identifies the node as a node which is part of a confinement area which should be recofigured to recover from the error reported in the error report message.

摘要翻译： 在由具有相应的错误报告和控制线（106）的处理器总线（105）组成的矩阵中提供了许多智能节点（总线接口单元-IBU和存储器控制单元-MCU）。 和具有对应的错误报告和控制线（108）的存储器总线（107）。 错误检测机制处理跨越区域边界的信息流。 每个节点（100,101,102,103）具有用于在错误报告行（106,108）上记录错误和报告错误的装置。 如果存在错误的节点发生错误，则会发出在所有节点的错误报告行上接收和重新传播的错误消息。 错误消息标识错误的类型和检测到错误的节点ID。 一个节点中的限制区域隔离逻辑将错误报告消息中的节点ID标识为作为故障限制区域的一部分的节点，从而隔离节点是其中一部分的故障限制区域。 节点中的逻辑重新配置系统的至少一部分，条件是错误报告消息中的节点ID将节点标识为节点，该节点是应重新配置的节点，以从错误报告中报告的错误中恢复 信息。

公开(公告)号：US4503534A

公开(公告)日：1985-03-05

申请号：US393905

申请日：1982-06-30

申请人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

发明人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

IPC分类号： G06F11/00

CPC分类号： G06F11/1629 ,  G06F11/0724 ,  G06F11/0763 ,  G06F11/165 ,  G06F11/1666 ,  G06F11/1658 ,  G06F11/1675

摘要： A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error-report lines (106, 108). Processor modules (110) and memory modules (112) are each connected to a node which controls access to a common memory bus (107). Each node includes means (a married bit-170 and a shadow bit-172) for marrying modules in pairs such that each module in the pair tracks the operations directed to the module pair, and each module in the pair alternates with the other module in the handling of requests or replies. Each node registers the ID of the other node in a spouse ID register. Comparison logic (162, 164) in each node resets the married bit upon the condition that the node ID (identifying the node at which the error occurred) in an error-report message is equal to the ID stored in the spouse ID register, thus identifying the spouse node (the partner of the node in which the comparison logic is located) as the source of the error. Resetting the married bit splits apart the primary/shadow pair, so that the error-free module takes over and ceases to alternate with its partner.

摘要翻译： 在由具有相应的错误报告和控制线（106）的处理器总线（105）组成的矩阵中提供了许多智能节点（总线接口单元-IBU和存储器控制单元-MCU）。 和具有对应的错误报告和控制线（108）的存储器总线（107）。 每个节点（100,101,102,103）具有用于在错误报告行（106,108）上记录错误和报告错误的装置。 处理器模块（110）和存储器模块（112）各自连接到控制对公共存储器总线（107）的访问的节点。 每个节点包括用于成对结合模块的装置（已婚的位170和影子位172），使得该对中的每个模块跟踪针对模块对的操作，并且该对中的每个模块与另一模块中的每个模块交替 处理请求或回复。 每个节点在配偶ID寄存器中注册另一个节点的ID。 每个节点中的比较逻辑（162,164）在错误报告消息中识别发生错误的节点ID等于配偶ID寄存器中存储的ID的条件下重置已婚比特，因此 识别配偶节点（比较逻辑所在的节点的伙伴）作为错误的来源。 重新设置已拆分的主分割主体/阴影对，使得无错误的模块接管并停止与其伙伴交替使用。

公开(公告)号：US4438494A

公开(公告)日：1984-03-20

申请号：US296025

申请日：1981-08-25

申请人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  Brad W. Hosler ,  David B. Johnson ,  Craig B. Peterson

发明人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  Brad W. Hosler ,  David B. Johnson ,  Craig B. Peterson

IPC分类号： G06F11/20 ,  G06F11/07 ,  G06F11/00

CPC分类号： G06F11/0772 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0784 ,  G06F11/0793

摘要： A number of intelligent crossbar switches (100) are provided in a matrix of orthogonal lines interconnecting processor (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding error-reporting lines (106); and memory buses (107) with corresponding error-reporting lines (108). At the intersection of these lines is a crossbar switch node (100). The crossbar switches function to pass memory requests from a processor to a memory module attached to an MCU node and to pass any data associated with the requests. The system is organized into confinement areas at the boundaries of which are positioned error-detection mechanisms to deal with information flow occurring across area boundaries. Each crossbar switch and MCU node has means for the logging and signaling of errors to other nodes. Means are provided to reconfigure the system to reroute traffic around the confinement area at fault and for restarting system operation in a possibly degraded mode.

摘要翻译： 在互连处理器（110）和存储器控制单元（MCU）模块（112）的正交线的矩阵中提供了许多智能交叉开关（100）。 矩阵由处理器总线（105）和相应的错误报告线（106）组成。 和具有对应的错误报告行（108）的存储器总线（107）。 这些线路的交叉点是交叉开关节点（100）。 交叉开关用于将存储器请求从处理器传递到连接到MCU节点的存储器模块，并传递与请求相关联的任何数据。 系统被组织成限制区域，其边界位于错误检测机制中，以处理跨区域边界发生的信息流。 每个交叉开关和MCU节点都有用于记录和向其他节点发送错误信号的手段。 提供了用于重新配置系统以重新路由处于故障的限制区域周围的业务并且以可能降级的模式重新启动系统操作的手段。

公开(公告)号：US06317803B1

公开(公告)日：2001-11-13

申请号：US08721893

申请日：1996-09-27

申请人： Norman J. Rasmussen ,  Gary A. Solomon ,  David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case

发明人： Norman J. Rasmussen ,  Gary A. Solomon ,  David G. Carson ,  George R. Hayek ,  Brent S. Baxter ,  Colyn Case

IPC分类号： G06F1300

CPC分类号： G06F13/1615 ,  G06F13/161 ,  G06F13/1631

摘要： A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

摘要翻译： 提供了高吞吐量的存储器访问端口。 该端口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该端口允许内存读取和写入请求流水线，以隐藏内存访问延迟的影响。 特别地，端口允许以非流水线模式（例如由PCI提供）或以流水线模式执行总线事务。 在流水线模式中，允许在第一存储器访问请求和其对应的数据传送之间插入一个或多个附加存储器访问请求。 相比之下，在非流水线模式下，不能在第一存储器访问请求和其对应的数据传输之间插入附加存储器访问请求。

公开(公告)号：US4829425A

公开(公告)日：1989-05-09

申请号：US168635

申请日：1988-03-01

申请人： William L. Bain, Jr. ,  David G. Carson ,  George W. Cox ,  Robert C. Duzett ,  Brad W. Hosler ,  Scott A. Ogilvie ,  Craig B. Peterson ,  John L. Wipfli

发明人： William L. Bain, Jr. ,  David G. Carson ,  George W. Cox ,  Robert C. Duzett ,  Brad W. Hosler ,  Scott A. Ogilvie ,  Craig B. Peterson ,  John L. Wipfli

IPC分类号： G06F13/40

CPC分类号： G06F13/404

摘要： An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers. The register-set pointers map between logical addresses used in the instructions of the tasks used to access the pointers and physical register-set addresses used to access the register. Programmed logic in each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer dynamically allocate the register sets to the sending and destination tasks.

摘要翻译： 用于控制本地总线和I / O总线之间的数据传输的I / O处理器。 执行单元，I / O总线排序器和本地总线顺控程序连接到寄存器文件。 寄存器文件被均匀地寻址，执行单元，本地总线排序器和I / O总线排序器中的每一个具有对寄存器文件的读/写访问。 寄存器文件由多个寄存器组构成。 执行单元包括编程处理器，其被编程为通过在消息形式的任务之间传递寄存器集描述符来在处理器上运行的任务之间分配寄存器集。 本地总线定序器包括面向分组的多处理器总线，每个分组中存在可变数量的字节。 I / O定序器包括用于在I / O总线和寄存器文件之间以总线相关数据速率对数据进行多字节排序的逻辑。 每个任务包括任务帧，每个任务帧包括寄存器集指针。 寄存器集指针映射在用于访问指针的任务的指令中使用的逻辑地址和用于访问寄存器的物理寄存器集地址之间。 每个执行单元，本地总线排序器和I / O总线顺控程序中的程序逻辑动态地将寄存器组分配给发送和目标任务。

公开(公告)号：US4480307A

公开(公告)日：1984-10-30

申请号：US336866

申请日：1982-01-04

申请人： David L. Budde ,  David G. Carson ,  David B. Johnson ,  Doran K. Wilde

发明人： David L. Budde ,  David G. Carson ,  David B. Johnson ,  Doran K. Wilde

IPC分类号： G06F13/16 ,  G06F13/00

CPC分类号： G06F13/1615

摘要： A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and read-request packets are issued to the memory-control unit. The memory-control unit responds with reply packets. A message controller (416), bus monitor (413), and pipeline and reply monitor ( 414), run the memory bus in a three-level pipeline mode. There may be three outstanding requests in the bus pipeline. Any further requests must wait for a reply message to free-up a slot in the pipeline before proceeding. Request messages increase the length of the pipeline and reply messages decrease the length of a pipeline. A control message, called a blurb, does not affect the pipeline length and can be issued when the pipeline is not full. The different messages are distinguished by three control signals (405) that parallel the data portion of the bus. The message generator (417) and interface logic (404) drive these control lines to indicate the message type, the start and end of the message, and possible error conditions. The pipeline and reply monitor (414) and the message controller (416) cooperate to insert a reply to a particular request in the pipeline position corresponding to the particular request that invoked the reply.