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公开(公告)号：US5758169A
公开(公告)日：1998-05-26
申请号：US868370
申请日：1997-06-03
申请人： P. K. Nizar , David Carson
发明人： P. K. Nizar , David Carson
CPC分类号： G06F9/4818 , G06F13/24 , G06F13/26 , G06F15/17
摘要： A multi-processor system includes an interrupt bus used for arbitrating among eligible processors to determine which processor is to service of an interrupt request. The interrupt bus comprises wired-OR connection data lines that are used for arbitration. A local interrupt controller that handles the acceptance of interrupt request messages on the interrupt bus is associated with each processor. To minimize interruption of high priority tasks, interrupts can be accepted by the processor in the system that is currently running the lowest priority task. An arbitration protocol governs the interrupt bus and determines the lowest priority processor. The arbitration protocol includes choosing one among the lowest priority processors by means of a random priority scheme that uses an arbitration ID that is updated with each message.
摘要翻译： 多处理器系统包括用于在合格处理器之间仲裁的中断总线，以确定哪个处理器将服务于中断请求。 中断总线包括用于仲裁的有线OR连接数据线。 处理在中断总线上接受中断请求消息的本地中断控制器与每个处理器相关联。 为了最大限度地减少高优先级任务的中断，当前运行最低优先级任务的系统中的处理器可以接受中断。 仲裁协议控制中断总线并确定最低优先级处理器。 仲裁协议包括通过采用随每个消息更新的仲裁ID的随机优先级方案来选择最低优先级处理器之一。
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2.发明授权Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller 失效可编程多处理器中断控制器系统，具有处理器集成的局部中断控制器
公开(公告)号：US5613128A
公开(公告)日：1997-03-18
申请号：US643734
申请日：1996-05-06
申请人： P. K. Nizar , David Carson
发明人： P. K. Nizar , David Carson
CPC分类号： G06F9/4818 , G06F13/24 , G06F13/26 , G06F15/17
摘要： A multi-processor programmable interrupt controller system that includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for bus and priority arbitration, using a standard message format and arbitration protocol. The system is implemented, in part, by incorporating the processor interrupt controller with its associated processor into a single integrated circuit. The common system bus which normally carries all system traffic is not used for interrupt request messages. The interrupt controller bus is used for this purpose and thus results in a more efficient system by relieving the system bus of interrupt service requests and the related interrupt request traffic.
摘要翻译： 一种多处理器可编程中断控制器系统，包括：I / O中断控制器，用于从I / O子系统接收中断请求; 多个处理器中断控制器，每个与特定处理器相关联，用于分配接受的中断; 以及主要用于在中断控制器单元之间传输中断请求以及用于总线和优先级仲裁的中断控制器总线，使用标准消息格式和仲裁协议。 该系统部分地通过将处理器中断控制器与其相关联的处理器并入单个集成电路中来实现。 通常承载所有系统流量的公共系统总线不用于中断请求消息。 中断控制器总线用于此目的，从而通过减轻系统总线的中断服务请求和相关的中断请求流量来实现更有效的系统。
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3.发明授权Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems 失效多处理器可编程中断控制器系统适用于功能冗余校验处理器系统
公开(公告)号：US5410710A
公开(公告)日：1995-04-25
申请号：US176136
申请日：1993-12-30
摘要： A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a subharmonic of the FRC unit master CPU clock, for handling interrupt request (IRQ) related messages and maintaining synchronism between the master and checker CPUs of the FRC unit. Additional embodiments provide for the use of D-type flip-flop synchronizers to accommodate FRC units whose internal (core) clock or external bus clock are not harmonically related to the interrupt clock frequency. Each processor unit has an interrupt acceptance unit (IAU) coupled to the interrupt bus for the acceptance of IRQs and for broadcasting of IRQs generated by its associated on-chip processor. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two data wires for 2-bit parallel-serial data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to the lowest priority mode arbitration procedure also provides for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus.
摘要翻译： 一种用于多处理器系统的多处理器可编程中断控制器系统，其中一个处理器单元是功能冗余校验（FRC）单元，具有与系统（存储器）总线不同的同步中断总线，具有中断总线时钟 频率是FRC单元主CPU时钟的次谐波，用于处理中断请求（IRQ）相关消息，并保持FRC单元的主站和检查CPU之间的同步。 另外的实施例提供使用D型触发器同步器来容纳其内部（核心）时钟或外部总线时钟与中断时钟频率没有谐波相关性的FRC单元。 每个处理器单元具有耦合到中断总线的中断接受单元（IAU），用于接收IRQ和用于广播由其相关联的片上处理器产生的IRQ。 I / O设备中断线连接到一个或多个中断传送单元（IDU），每个中断传送单元都连接到中断总线，用于广播I / O生成的IRQ。 中断总线是一个同步三线总线，具有一个时钟线和两个数据线用于2位并行 - 串行数据传输。 用于由IAU和IDU控制中断总线的仲裁使用数据线之一。 最低优先级IRQ传递模式使用类似的单线仲裁程序来确定哪个IAU具有在其相关的片上处理器中运行的最低当前优先级任务。 对最优先权模式仲裁程序的修改还规定了IRQ向符合条件的处理器的均匀分配。 IRQ的实际服务是通过系统总线完成的。
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4.发明授权Multiprocessor interrupt controller with remote reading of interrupt control registers 失效具有远程读取中断控制寄存器的多处理器中断控制器
公开(公告)号：US5495615A
公开(公告)日：1996-02-27
申请号：US176122
申请日：1993-12-30
申请人： P. K. Nizar , David G. Carson , Adi Golbert , David Finzi , Yoav Hochberg
发明人： P. K. Nizar , David G. Carson , Adi Golbert , David Finzi , Yoav Hochberg
摘要： A multiprocessor programmable interrupt controller (MPIC) system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt-related messages. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated interrupt request messages. Each processor chip has an on-board interrupt acceptance unit (IAU) that can accept interrupt requests from the interrupt bus and can broadcast on the interrupt bus interrupt request messages generated by its associated processor. Each processor can request to read the contents of the IAU control registers that are associated with another target processor. In that case, a remote read request message is generated by the IAU of the local processor and responded to, without software intervention, by the IAU of the target processor. A remote read status field indicates to the local processor the status of the data contained in a remote read register. The remote IAU is expected to respond in a fixed number of interrupt bus cycles. If the remote agent is unable to do so, then the remote read status field becomes "Invalid." If successful, the remote read status resolves to "Valid." The processor polls this field to determine the completion and success of the remote read request. Remote read requests are always successful (although the data may be valid or invalid) in that they are never retried. Remote read requests are primarily a debug feature, and a "hung" remote IAU that is unable to respond to a remote read request should not cause the debugging software to hang on the local processor.
摘要翻译： 多处理器可编程中断控制器（MPIC）系统具有与系统（存储器）总线不同的中断总线，用于处理与中断有关的消息。 I / O设备中断线连接到一个或多个中断传送单元（IDU），每个中断传送单元都连接到中断总线，用于广播I / O生成的中断请求消息。 每个处理器芯片都有一个板载中断接受单元（IAU），可以接受来自中断总线的中断请求，并可以在中断总线上广播由其关联的处理器生成的中断请求消息。 每个处理器可以请求读取与另一个目标处理器相关联的IAU控制寄存器的内容。 在这种情况下，远程读取请求消息由本地处理器的IAU生成，并且由目标处理器的IAU在没有软件干预的情况下进行响应。 远程读取状态字段向本地处理器指示包含在远程读取寄存器中的数据的状态。 远程IAU预计将以固定数量的中断总线周期进行响应。 如果远程代理不能这样做，则远程读取状态字段变为“无效”。 如果成功，则远程读取状态解析为“有效”。 处理器轮询此字段以确定远程读取请求的完成和成功。 远程读取请求始终是成功的（尽管数据可能是有效的或无效的），因为它们不会被重试。 远程读取请求主要是调试功能，无法响应远程读取请求的“挂起”远程IAU不应导致调试软件挂起在本地处理器上。
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5.发明授权Multi-processor computer system with interrupt controllers providing remote reading 失效具有中断控制器的多处理器计算机系统提供远程读取
公开(公告)号：US5701496A
公开(公告)日：1997-12-23
申请号：US710451
申请日：1996-09-17
申请人： P. K. Nizar , David Carson
发明人： P. K. Nizar , David Carson
CPC分类号： G06F9/4818 , G06F13/24 , G06F13/26 , G06F15/17
摘要： A multi-processor programmable interrupt controller system that includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for bus and priority arbitration, using a standard message format and arbitration protocol. The system is implemented, in part, by incorporating the processor interrupt controller with its associated processor into a single integrated circuit. The common system bus which normally carries all system traffic is not used for interrupt request messages. The interrupt controller bus is used for this purpose and thus results in a more efficient system by relieving the system bus of interrupt service requests and the related interrupt request traffic.
摘要翻译： 一种多处理器可编程中断控制器系统，包括：I / O中断控制器，用于从I / O子系统接收中断请求; 多个处理器中断控制器，每个与特定处理器相关联，用于分配接受的中断; 以及主要用于在中断控制器单元之间传输中断请求以及用于总线和优先级仲裁的中断控制器总线，使用标准消息格式和仲裁协议。 该系统部分地通过将处理器中断控制器与其相关联的处理器并入单个集成电路中来实现。 通常承载所有系统流量的公共系统总线不用于中断请求消息。 中断控制器总线用于此目的，从而通过减轻系统总线的中断服务请求和相关的中断请求流量来实现更有效的系统。
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公开(公告)号：US5696976A
公开(公告)日：1997-12-09
申请号：US710452
申请日：1996-09-17
申请人： P. K. Nizar , David Carson
发明人： P. K. Nizar , David Carson
CPC分类号： G06F9/4818 , G06F13/24 , G06F13/26 , G06F15/17
摘要： A multi-processor system includes an interrupt bus used for arbitrating among eligible processors to determine which processor is to service of an interrupt request. The interrupt bus comprises wired-OR connection data lines that are used for arbitration. A local interrupt controller that handles the acceptance of interrupt request messages on the interrupt bus is associated with each processor. To minimize interruption of high priority tasks, interrupts can be accepted by the processor in the system that is currently running the lowest priority task. An arbitration protocol governs the interrupt bus and determines the lowest priority processor. The arbitration protocol includes choosing one among the lowest priority processors by means of a random priority scheme that uses an arbitration ID that is updated with each message.
摘要翻译： 多处理器系统包括用于在合格处理器之间仲裁的中断总线，以确定哪个处理器将服务于中断请求。 中断总线包括用于仲裁的有线OR连接数据线。 处理在中断总线上接受中断请求消息的本地中断控制器与每个处理器相关联。 为了最大限度地减少高优先级任务的中断，当前运行最低优先级任务的系统中的处理器可以接受中断。 仲裁协议控制中断总线并确定最低优先级处理器。 仲裁协议包括通过采用随每个消息更新的仲裁ID的随机优先级方案来选择最低优先级处理器之一。
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7.发明授权Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management 失效具有单独中断总线和总线重试管理的多处理器可编程中断控制器系统
公开(公告)号：US5555420A
公开(公告)日：1996-09-10
申请号：US175776
申请日：1993-12-30
摘要： A multiprocessor programmable interrupt controller system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt request (IRQ) related messages. Each processor chip has an on-board interrupt acceptance unit (IAU) coupled to the interrupt bus to accept IRQs and to broadcast IRQs that it generates. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus to broadcast I/O-generated IRQs. The interrupt bus is a synchronous three-wire bus having one clock wire and two wires for data transmission. Arbitration for control of the interrupt bus by the IAUs and IDUs uses one of the data wires. Lowest priority IRQ delivery mode uses a similar one-wire arbitration procedure for determining which IAU has the lowest current priority task running in its associated on-chip processor. A modification to this procedure also provides uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done via the system bus. IAU acceptance logic is minimized by allowing retry of a delivered message when the acceptance latches are full. The increase in interrupt bus traffic due to retry is minimized by controlling the time intervals between rebroadcasts of unaccepted IRQs. Exponential timers control this interval so that each succeeding interval is a multiplicative factor, typically 2, greater than the preceding interval.
摘要翻译： 多处理器可编程中断控制器系统具有与系统（存储器）总线不同的中断总线，用于处理与中断请求（IRQ）相关的消息。 每个处理器芯片具有耦合到中断总线的板载中断接受单元（IAU），以接收IRQ并广播其产生的IRQ。 I / O设备中断线连接到一个或多个中断传送单元（IDU），每个中断传送单元都连接到中断总线以广播I / O生成的IRQ。 中断总线是一个同步三线总线，具有一个时钟线和两条数据传输线。 用于由IAU和IDU控制中断总线的仲裁使用数据线之一。 最低优先级IRQ传递模式使用类似的单线仲裁程序来确定哪个IAU具有在其相关的片上处理器中运行的最低当前优先级任务。 对此程序的修改还可以将IRQ统一分配给符合条件的处理器。 IRQ的实际服务通过系统总线完成。 当接收锁存器已满时，允许重传所传送的消息，IAU接受逻辑被最小化。 通过控制不接受的IRQ的重播之间的时间间隔，可以最大限度地减少因重试引起的中断总线流量的增加。 指数定时器控制此间隔，以便每个后续间隔是乘法因子，通常为2，大于前一个间隔。
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