公开(公告)号：US5633915A

公开(公告)日：1997-05-27

申请号：US442336

申请日：1995-05-16

Applicant: Cheng Yang ,  David W. Matula

Inventor： Cheng Yang ,  David W. Matula

IPC: H04W16/06 ,  H04W16/32 ,  H04Q7/22

CPC classification number: H04W16/06 ,  H04W16/32 ,  H04W28/08 ,  H04W72/0413 ,  H04W72/0453

Abstract: A multiple-layered cellular communication system particularly adapted to mobile phones and LAN type communication is provided with an overlaid arrangement of cell transceivers. By having this overlay, multiple service providers can provide a cooperative method of load sharing. The usage of the frequency spectrum can be improved and an advanced hand-off arrangement can be used to prevent or reduce the possibility of blocked calls due to cell saturation.

Abstract translation: 特别适用于移动电话和LAN类型通信的多层蜂窝通信系统被提供有小区收发机的重叠布置。 通过拥有这种覆盖，多个服务提供商可以提供负载共享的协作方法。 可以提高频谱的使用，并且可以使用先进的切换装置来防止或减少由于信元饱和而阻塞呼叫的可能性。

公开(公告)号：US5159566A

公开(公告)日：1992-10-27

申请号：US852917

申请日：1992-03-13

Applicant: Willard S. Briggs ,  Thomas B. Brightman ,  David W. Matula

Inventor： Willard S. Briggs ,  Thomas B. Brightman ,  David W. Matula

IPC: G06F7/552

CPC classification number: G06F7/5525

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.

Abstract translation: 一种用于执行平方根函数的方法和装置，其首先包括近似操作数的平方根的短倒数。 将相应的偏差调整因子添加到近似值中，并将结果截断以形成正确偏置的短倒数。 然后将该短互逆乘以操作数的预定数量的最高有效位，并且将产品适当地截断以产生第一根数值。 乘法发生在具有矩形方面的乘法器阵列中，其中长边具有基本上与期望的全精度根所需的位数一样大的位数。 乘法器阵列的短边比单个根数值所需的位数多几个保护位的位数稍大一些，这也被确定为短倒数中的位数。 根数值平方，并从操作数中减去精确的平方，以产生精确的余数。 通过将短倒数乘以适当移位的电流余数来确定新的根数值，选择性地添加数字偏差调整因子并截断产品。 根数值被适当地移位和累加以形成部分根。 重复描述的步骤以连续地产生具有相应新的精确余数的根数值和部分根。

公开(公告)号：US08060550B2

公开(公告)日：2011-11-15

申请号：US11535607

申请日：2006-09-27

Applicant: Alexandru Fit-Florea ,  David W. Matula

Inventor： Alexandru Fit-Florea ,  David W. Matula

IPC: G06F1/02 ,  G06F7/00 ,  G06F7/38 ,  G06F15/00

CPC classification number: G06F7/72 ,  G06F1/0307

Abstract: Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.

Abstract translation: 转换整数包括接收整数，其中整数可以表示为模数分解。 模因式分解包括一个或多个因素，其中每个因子具有指数。 整数表示为残差的乘积。 从对应于残差乘积的和建立整数的离散对数。 从离散对数确定因子指数的值。 该整数表示为包含一个或多个因子的模因式分解，其中每个因子具有指数的值。

公开(公告)号：US07962537B2

公开(公告)日：2011-06-14

申请号：US11768742

申请日：2007-06-26

Applicant: David W. Matula ,  Mitchell A. Thornton ,  Alexandru Fit-Florea ,  Lun Li

Inventor： David W. Matula ,  Mitchell A. Thornton ,  Alexandru Fit-Florea ,  Lun Li

IPC: G06F7/00

CPC classification number: G06F1/0353 ,  G06F2101/10

Abstract: Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and the subset represents a subtree of the hierarchical tree. Bit fields are selected from the subset, and bits are extracted from the bit fields. A table output is determined from the extracted bits.

Abstract translation: 确定代表整数值函数的层次树的表的表输出包括从表输入确定地址。 根据地址选择存储器的子集，其中存储器表示分层树，并且子集表示层次树的子树。 从子集中选择位字段，并从位字段中提取位。 从提取的比特确定表输出。

公开(公告)号：US06978289B1

公开(公告)日：2005-12-20

申请号：US10108251

申请日：2002-03-26

Applicant: David W. Matula

Inventor： David W. Matula

IPC: G06F7/38 ,  G06F17/17

CPC classification number: G06F17/17

Abstract: An apparatus and method are disclosed for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials. Unlike prior art methods that individually round each polynomial coefficient of a function, the method of the present invention use a “ripple carry” rounding method to round each coefficient using information from the previously rounded coefficient. The “ripple carry” method generates rounded coefficients that significantly improve the total rounding error for the function.

Abstract translation: 公开了一种用于最小化用于内插多项式的查找表中的系数值中的累积舍入误差的装置和方法。 不同于对功能的各个多项式系数进行单独舍入的现有技术方法，本发明的方法使用“波动进位”舍入方法来舍入每个系数，使用来自先前舍入系数的信息。 “纹波进位”方法产生圆整系数，显着提高了该函数的总舍入误差。

公开(公告)号：US06782405B1

公开(公告)日：2004-08-24

申请号：US09876786

申请日：2001-06-07

Applicant: David W. Matula ,  Cristina S. Iordache

Inventor： David W. Matula ,  Cristina S. Iordache

IPC: G06F744

CPC classification number: G06F7/535 ,  G06F7/5525 ,  G06F2207/5354 ,  G06F2207/5356

Abstract: The division and square root systems include a multiplier. The systems also include a multipartite table system, a folding inverter, and a complement inverter, each coupled to the multiplier. The division and square root functions can be performed using three scaling iterations. The system first determines both a first and a second scaling value. The first scaling value is a semi-complement term computed using the folding inverter to invert selected bits of the input. The second scaling value is a table lookup value obtained from the multipartite table system. In the first iteration, the system scales the input by the semi-complement term. In the second iteration, the resulting approximation is scaled by a function of the table lookup value. In the third iteration, the approximation is scaled by a value obtained from a function of the semi-complement term and the table lookup value. After the third iteration, the approximation is available for rounding.

Abstract translation: 除法和平方根系统包括乘数。 该系统还包括一个多部分台系统，一个折叠逆变器和一个互补反相器，每个都耦合到该乘法器。 可以使用三次缩放迭代来执行除法和平方根函数。 系统首先确定第一和第二缩放值。 第一缩放值是使用折叠逆变器来计算输入的所选位的半补码项。 第二个缩放值是从多部分表系统获得的表查找值。 在第一次迭代中，系统将输入缩放为半补码项。 在第二次迭代中，所得到的近似由表查找值的函数进行缩放。 在第三次迭代中，通过从半补码项和表查找值的函数获得的值来缩放近似。 第三次迭代后，近似值可用于舍入。

公开(公告)号：US5060182A

公开(公告)日：1991-10-22

申请号：US402822

申请日：1989-09-05

Applicant: Willard S. Briggs ,  Thomas B. Brightman ,  David W. Matula

Inventor： Willard S. Briggs ,  Thomas B. Brightman ,  David W. Matula

IPC: G06F7/552

CPC classification number: G06F7/5525

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.