公开(公告)号：US5896573A

公开(公告)日：1999-04-20

申请号：US843186

申请日：1997-04-14

Applicant: Cheng Yang ,  David W. Matula

Inventor： Cheng Yang ,  David W. Matula

IPC: H04W16/06 ,  H04W16/32 ,  H04Q7/20

CPC classification number: H04W16/06 ,  H04W16/32 ,  H04W28/08 ,  H04W72/0413 ,  H04W72/0453

Abstract: Cellular communication systems supporting high utilization geographic regions having extensive cell overlap segments that collectively contain a substantial portion of the mobile units. A system and method for channel assignments incorporating selection from alternative transceivers defining overlapping cells is provided with load balancing to reduce call blocking. The system incorporates selective multiple handoffs responsive to channel assignment requests both to extend load balancing and also to substantially avoid call cutoff when active mobile units cross cell boundaries into possibly saturated cells.

Abstract translation: 蜂窝通信系统支持具有广泛小区重叠段的高利用率地理区域，其共同地包含移动单元的大部分。 提供了包含定义重叠小区的替代收发器的选择的信道分配的系统和方法，具有负载平衡以减少呼叫阻塞。 该系统包括响应于信道分配请求的选择性多次切换以扩展负载平衡，并且当活动移动单元跨越小区边界到可能的饱和小区时，基本上避免呼叫截止。

公开(公告)号：US5144576A

公开(公告)日：1992-09-01

申请号：US402798

申请日：1989-09-05

Applicant: Willard S. Briggs ,  David W. Matula

Inventor： Willard S. Briggs ,  David W. Matula

IPC: G06F7/52 ,  G06F7/48 ,  G06F7/506 ,  G06F7/53 ,  G06F7/533 ,  G06F7/535 ,  G06F7/552

CPC classification number: G06F7/4824

Abstract: A rectangular array signed digit multiplier circuit (10) is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), an A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, and ADDER INPUT and a FEEDBACK INPUT, respectively, The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

公开(公告)号：US5307303A

公开(公告)日：1994-04-26

申请号：US810710

申请日：1991-12-18

Applicant: Willard S. Briggs ,  David W. Matula

Inventor： Willard S. Briggs ,  David W. Matula

IPC: G06F7/491 ,  G06F7/52

CPC classification number: G06F7/4917 ,  G06F7/535 ,  G06F7/5375 ,  G06F2207/5351 ,  G06F2207/5355

Abstract: A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder. The described steps are repeated to serially generate quotient digit values with exact partial remainders with the preceding partial remainder taking the place of the dividend. The quotient digit values are accumulated to yield a complete quotient. The complete quotient is decremented and the remainder recalculated if the final partial remainder is negative, yield the full precision unique quotient and non-negative remainder pair.

Abstract translation: 描述了用于执行划分的方法和装置，其首先包括近似除数的短倒数。 将相应的偏置调整因子加到近似值中，并将正确偏置的短互逆乘以被除数的预定数量的最高有效位，并且产品被截断以产生第一商数位值。 乘法发生在具有矩形长宽比的乘法器阵列中，长边具有至少与除数所需的比特数一样大的比特数。 乘法器阵列的短边具有比单个商数值所需的位数多几个保护位的位数，其也被确定为短倒数中的位数。 商数值乘以完全除数，并从分红中减去确切产品，以产生精确的部分余数。 重复描述的步骤以用精确的部分余数串行地生成商数值，其中前面的部分余数取代了除数。 商数值被累积以产生一个完整的商。 如果最终的部分余数为负，则完整商减少，剩余部分重新计算，产生全精度唯一商和非负余数对。

公开(公告)号：US5184318A

公开(公告)日：1993-02-02

申请号：US813942

申请日：1991-12-24

Applicant: Willard S. Briggs ,  David W. Matula

Inventor： Willard S. Briggs ,  David W. Matula

IPC: G06F7/48

CPC classification number: G06F7/4824

Abstract: A rectangular array signed digit multiplier circuit 10 is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), and A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, an ADDER INPUT and a FEEDBACK INPUT, respectively. The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

Abstract translation: 公开了一种矩阵阵列有符号数乘法器电路10，其包括乘法器芯（28）。 电路（10）包括C锁存器（14），D锁存器（18）和A锁存器（26），反馈锁存器（52）可操作以存储要输入到乘法器内核（28）的操作数 ）分别通过MULTIPLIER INPUT，被乘数输入，ADDER INPUT和FEEDBACK INPUT输入。 由乘法器芯（28）输出的乘积可以包括通过MULTIPLIER INPUT和MULTIPLICAND INPUT输入的值与ADDER和FEEDBACK INPUTS的乘积之和。 产品被存储在结果锁存器（40）中，并且可以在通过使用具有反馈锁存器（52）的数据通路耦合结果锁存器（40）的后续通过乘法器内核（28）中使用。 乘法器核心（28）包括三次加法器电平（56），布朗编码器电平（58），部分乘积发生器电平（60），一级加法器电平（62），二级加法器电平 （64）和三级加法器级（66）。

公开(公告)号：US5046038A

公开(公告)日：1991-09-03

申请号：US389051

申请日：1989-08-02

Applicant: Willard B. Briggs ,  David W. Matula

Inventor： Willard B. Briggs ,  David W. Matula

IPC: G06F7/483 ,  G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F7/4917 ,  G06F7/5375 ,  G06F2207/5351 ,  G06F2207/5355

Abstract: A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder. The described steps are repeated to serially generate quotient digit values with exact partial remainders with the preceding partial remainder taking the place of the dividend. The quotient digit values are accumulated to yield a complete quotient. The complete quotient is decremented and the remainder recalculated if the final partial remainder is negative, yielding the full precision unique quotient and non-negative remainder pair.

Abstract translation: 描述了用于执行划分的方法和装置，其首先包括近似除数的短倒数。 将相应的偏置调整因子加到近似值中，并将正确偏置的短互逆乘以被除数的预定数量的最高有效位，并且产品被截断以产生第一商数位值。 乘法发生在具有矩形长宽比的乘法器阵列中，长边具有至少与除数所需的比特数一样大的比特数。 乘法器阵列的短边具有比单个商数值所需的位数多几个保护位的位数，其也被确定为短倒数中的位数。 商数值乘以完全除数，并从分红中减去确切产品，以产生精确的部分余数。 重复描述的步骤以用精确的部分余数串行地生成商数值，其中前面的部分余数取代了除数。 商数值被累积以产生一个完整的商。 如果最终部分余数为负，则完整商减少，并且余数重新计算，产生全精度唯一商和非负余数对。

公开(公告)号：US07543008B1

公开(公告)日：2009-06-02

申请号：US11115616

申请日：2005-04-27

Applicant: David W. Matula ,  Willard S. Briggs

Inventor： David W. Matula ,  Willard S. Briggs

IPC: G06F1/02 ,  G06F7/38

CPC classification number: G06F7/5338

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recoded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract translation: 公开了一种用于为数字查找表电路提供更高的基数冗余数字查找表的装置和方法。 压缩直接查找表单元访问能够提供高阶部分的冗余数字查找表和可以直接并入以形成输出数值的低阶部分。 本发明的冗余数字查找表被构造成不产生输出溢出异常。 还公开了能够将重新编码的输出值直接提供给乘法器单元的部分乘积生成器的冗余数字查找表编码器。

公开(公告)号：US06938062B1

公开(公告)日：2005-08-30

申请号：US10107598

申请日：2002-03-26

Applicant: David W. Matula ,  Willard S. Briggs

Inventor： David W. Matula ,  Willard S. Briggs

IPC: G06F7/38 ,  G06F7/533

CPC classification number: G06F7/5338

Abstract: An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recorded output values directly to partial product generators of a multiplier unit is also disclosed.

Abstract translation: 公开了一种用于为数字查找表电路提供更高的基数冗余数字查找表的装置和方法。 压缩直接查找表单元访问能够提供高阶部分的冗余数字查找表和可以直接并入以形成输出数值的低阶部分。 本发明的冗余数字查找表被构造成不产生输出溢出异常。 还公开了能够将记录的输出值直接提供给乘法器单元的部分乘积生成器的冗余数字查找表编码器。

公开(公告)号：US5633915A

公开(公告)日：1997-05-27

申请号：US442336

申请日：1995-05-16

Applicant: Cheng Yang ,  David W. Matula

Inventor： Cheng Yang ,  David W. Matula

IPC: H04W16/06 ,  H04W16/32 ,  H04Q7/22

CPC classification number: H04W16/06 ,  H04W16/32 ,  H04W28/08 ,  H04W72/0413 ,  H04W72/0453

Abstract: A multiple-layered cellular communication system particularly adapted to mobile phones and LAN type communication is provided with an overlaid arrangement of cell transceivers. By having this overlay, multiple service providers can provide a cooperative method of load sharing. The usage of the frequency spectrum can be improved and an advanced hand-off arrangement can be used to prevent or reduce the possibility of blocked calls due to cell saturation.

Abstract translation: 特别适用于移动电话和LAN类型通信的多层蜂窝通信系统被提供有小区收发机的重叠布置。 通过拥有这种覆盖，多个服务提供商可以提供负载共享的协作方法。 可以提高频谱的使用，并且可以使用先进的切换装置来防止或减少由于信元饱和而阻塞呼叫的可能性。

公开(公告)号：US5159566A

公开(公告)日：1992-10-27

申请号：US852917

申请日：1992-03-13

Applicant: Willard S. Briggs ,  Thomas B. Brightman ,  David W. Matula

Inventor： Willard S. Briggs ,  Thomas B. Brightman ,  David W. Matula

IPC: G06F7/552

CPC classification number: G06F7/5525

Abstract: A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.

Abstract translation: 一种用于执行平方根函数的方法和装置，其首先包括近似操作数的平方根的短倒数。 将相应的偏差调整因子添加到近似值中，并将结果截断以形成正确偏置的短倒数。 然后将该短互逆乘以操作数的预定数量的最高有效位，并且将产品适当地截断以产生第一根数值。 乘法发生在具有矩形方面的乘法器阵列中，其中长边具有基本上与期望的全精度根所需的位数一样大的位数。 乘法器阵列的短边比单个根数值所需的位数多几个保护位的位数稍大一些，这也被确定为短倒数中的位数。 根数值平方，并从操作数中减去精确的平方，以产生精确的余数。 通过将短倒数乘以适当移位的电流余数来确定新的根数值，选择性地添加数字偏差调整因子并截断产品。 根数值被适当地移位和累加以形成部分根。 重复描述的步骤以连续地产生具有相应新的精确余数的根数值和部分根。

公开(公告)号：US08060550B2

公开(公告)日：2011-11-15

申请号：US11535607

申请日：2006-09-27

Applicant: Alexandru Fit-Florea ,  David W. Matula

Inventor： Alexandru Fit-Florea ,  David W. Matula

IPC: G06F1/02 ,  G06F7/00 ,  G06F7/38 ,  G06F15/00

CPC classification number: G06F7/72 ,  G06F1/0307

Abstract: Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.

Abstract translation: 转换整数包括接收整数，其中整数可以表示为模数分解。 模因式分解包括一个或多个因素，其中每个因子具有指数。 整数表示为残差的乘积。 从对应于残差乘积的和建立整数的离散对数。 从离散对数确定因子指数的值。 该整数表示为包含一个或多个因子的模因式分解，其中每个因子具有指数的值。