公开(公告)号：US20060004928A1

公开(公告)日：2006-01-05

申请号：US10883518

申请日：2004-06-30

Applicant: Gary Hess ,  Robert Strong ,  Jeffrey Brown ,  Michael Derr

Inventor： Gary Hess ,  Robert Strong ,  Jeffrey Brown ,  Michael Derr

IPC: G06F13/00

CPC classification number: G06F21/71 ,  G06F21/10 ,  G06F21/78 ,  G06F21/82 ,  G06F2221/2101

Abstract: A method, apparatus, and system are disclosed. In one embodiment the method comprises determining whether a feature on a device is permitted to be enabled, determining whether a total number of enabled features on the device is less than or equal to a maximum number of allowable features on the device, and allowing the enabling of the device feature if the device feature is permitted to be enabled and the total number of enabled features on the device is less than or equal to the maximum number of allowable features on the device.

公开(公告)号：US20060224803A1

公开(公告)日：2006-10-05

申请号：US11096941

申请日：2005-03-31

Applicant: Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

Inventor： Amir Zinaty ,  Adit Tarmaster ,  Michael Derr ,  Haim Lustig

IPC: G06F13/00

CPC classification number: G06F13/4291

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.

公开(公告)号：US20050182869A1

公开(公告)日：2005-08-18

申请号：US10781512

申请日：2004-02-17

Applicant: Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

Inventor： Chee Lee ,  Vui Liew ,  Mikal Hunsaker ,  Michael Derr

IPC: G06F3/00

CPC classification number: G06F12/0638

Abstract: A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O controller. The patch module is used to sample incoming cycles received by the I/O controller and to determine if the captured incoming cycle matches one or more of preprogrammed trigger conditions. The patch module is capable of working around a captured non-posted request cycle by controlling header information loaded into the completion queue and by instructing the completion queue whether or not to discard a completion received from a designated end-device.

Abstract translation: 描述了一种系统，用于在输入/输出（I / O）控制器内提供补丁机制，可用于解决I / O控制器中存在的缺陷和状况。 该系统包括耦合到包括在I / O控制器中的完成队列的补丁模块。 补丁模块用于对I / O控制器接收的进入周期进行采样，并确定捕获的进入周期是否匹配一个或多个预编程触发条件。 补丁模块能够通过控制加载到完成队列中的头信息并通过指示完成队列来确定是否丢弃从指定的终端设备接收到的完成，来围绕捕获的非发布请求周期进行操作。

公开(公告)号：US5860112A

公开(公告)日：1999-01-12

申请号：US579116

申请日：1995-12-27

Applicant: Brian K. Langendorf ,  Michael Derr

Inventor： Brian K. Langendorf ,  Michael Derr

IPC: G06F12/08

CPC classification number: G06F12/0804

Abstract: Apparatus and a method for utilizing a memory bus write buffer to blend up-to-date data stored in a processor cache and being written back to memory with data in the write buffer being written to the same memory address by a bus master in order to maintain data coherency. The circuitry also utilizes the memory bus write buffer to write valid data furnished in a bus master write over up-to-date data in the write buffer being written to the same memory address from a processor cache in order to maintain data coherency. Combining the data from the two sources prior to writing it to memory eliminates at least one write operation by the write controller along with any associated ECC value generation, may eliminate a number of read/modify/write back operations with any associated ECC value generations, and can double the effective depth of the buffer.

Abstract translation: 一种用于利用存储器总线写入缓冲器来混合存储在处理器高速缓存中的最新数据并被写回到存储器的方法，其中写入缓冲器中的数据被总线主机写入相同的存储器地址，以便 维护数据一致性。 该电路还利用存储器总线写入缓冲器来写入在总线主机中提供的有效数据，写入缓冲器中的最新数据被写入来自处理器高速缓存的相同存储器地址，以便保持数据一致性。 在写入存储器之前将来自两个源的数据组合，消除了写入控制器至少一次写入操作以及任何相关联的ECC值生成，可以消除与任何相关联的ECC值代的多个读取/修改/回写操作， 并可以将缓冲区的有效深度加倍。