公开(公告)号：US20190258539A1

公开(公告)日：2019-08-22

申请号：US16398076

申请日：2019-04-29

申请人： Zhenyu Zhu ,  William A. Stevens, JR. ,  Michael T. Klinglesmith ,  Mikal Hunsaker

发明人： Zhenyu Zhu ,  William A. Stevens, JR. ,  Michael T. Klinglesmith ,  Mikal Hunsaker

IPC分类号： G06F11/10 ,  G06F13/42 ,  G06F13/16

摘要： Embodiments include a serial bus controller that may be coupled to an in band serial peripheral interface (SPI) link, to request a write of data and a subsequent read of the data from a slave device and in response to the request to read the data, receive a bit error report and optionally correct the bit error over the in band SPI link. Embodiments include a slave device, e.g., a flash memory device, to detect and report the bit error over the in band SPI link, where the flash memory device, in response to a request to write and/or erase data, calculates or determines an error correction code (ECC) and stores corresponding parity data. In embodiments, after receiving a subsequent request to read the data, the flash memory device accesses the stored parity data to check the ECC for a bit error and if a bit error is detected, reports the detected bit error over the in band SPI link. Other embodiments may be described and claimed.

公开(公告)号：US20140181356A1

公开(公告)日：2014-06-26

申请号：US14194893

申请日：2014-03-03

申请人： Ting Lok Song ,  Su Wei Lim ,  Mikal Hunsaker ,  Hooi Kar Loo

发明人： Ting Lok Song ,  Su Wei Lim ,  Mikal Hunsaker ,  Hooi Kar Loo

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

公开(公告)号：US08185072B2

公开(公告)日：2012-05-22

申请号：US11690759

申请日：2007-03-23

申请人： Mikal Hunsaker ,  Karthi R. Vadivelu

发明人： Mikal Hunsaker ,  Karthi R. Vadivelu

IPC分类号： H04B1/10

CPC分类号： H04L12/12 ,  Y02D50/40

摘要： A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.

摘要翻译： 一种用于接收多个定义状态的接收机电路的功率降低方案，并且屏蔽逻辑以屏蔽静噪接收机的输出。 此外，该提案利用计数器来计数各种超时条件。 因此，静噪接收器消耗较少的功率，并且可以断电或周期性地允许轮询。

公开(公告)号：US20080313478A1

公开(公告)日：2008-12-18

申请号：US11763635

申请日：2007-06-15

申请人： Wong Kar Leong ,  Mikal Hunsaker

发明人： Wong Kar Leong ,  Mikal Hunsaker

IPC分类号： G06F1/00

CPC分类号： G06F1/10

摘要： An apparatus, method, and system are disclosed. In one embodiment, the apparatus includes a clock source unit that generates a clock signal, multiple clock trunk lines that supply the clock signal to multiple devices, and a clock control unit that instructs the clock source unit that can gate or supply the clock signal on the clock trunk lines.

摘要翻译： 公开了一种装置，方法和系统。 在一个实施例中，该装置包括产生时钟信号的时钟源单元，向多个设备提供时钟信号的多个时钟干线，以及指示可以对时钟信号进行门控或提供时钟信号的时钟源单元的时钟控制单元 时钟干线。

公开(公告)号：US20080072098A1

公开(公告)日：2008-03-20

申请号：US11524849

申请日：2006-09-20

申请人： Mikal Hunsaker ,  Karthi Vadivelu

发明人： Mikal Hunsaker ,  Karthi Vadivelu

IPC分类号： H04L12/28 ,  G06F3/00

CPC分类号： H04L12/40 ,  H04L12/40013 ,  H04L47/10 ,  H04L47/39

摘要： An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

摘要翻译： 本发明的实施例是有效的互连总线。 第一时钟源在链路总线上以与要发送到设备的第一数据同步的第一频率产生第一时钟信号。 当设备发送第二数据时，该设备具有第二时钟源，以与第二数据同步的第二频率生成第二时钟信号。 第一和第二数据每个形成作为发布的，完成的和未发布的数据包之一的数据包。 第一和第二频率彼此独立，分别在第一和第二频率范围内。 队列结构存储在基于信用的流量控制策略中使用的分组。

公开(公告)号：US08706944B2

公开(公告)日：2014-04-22

申请号：US12928906

申请日：2010-12-22

申请人： Ting Lok Song ,  Su Wei Lim ,  Mikal Hunsaker ,  Hooi Kar Loo

发明人： Ting Lok Song ,  Su Wei Lim ,  Mikal Hunsaker ,  Hooi Kar Loo

IPC分类号： G06F13/20 ,  G06F13/38

CPC分类号： G06F13/4022 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4282

摘要： In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

摘要翻译： 在一些实施例中，电子系统包括处理器，与处理器通信的存储器，与处理器通信的总线，耦合到总线的Express卡控制器，提供与外部设备的接口的Express卡控制器，USB3 控制器耦合到总线并与Express卡控制器通信，以及耦合到总线并与Express卡控制器通信的PCIE控制器。 Express卡控制器可以被配置为基于USB3选择引脚带的状态来确定外部设备是USB3设备还是PCIE设备，并且在USB3控制器和PCIE控制器之间切换。 公开和要求保护其他实施例。

公开(公告)号：US20080233912A1

公开(公告)日：2008-09-25

申请号：US11690759

申请日：2007-03-23

申请人： Mikal Hunsaker ,  Karthi R. Vadivelu

发明人： Mikal Hunsaker ,  Karthi R. Vadivelu

IPC分类号： H04B1/10

CPC分类号： H04L12/12 ,  Y02D50/40

摘要： A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.

摘要翻译： 一种用于接收多个定义状态的接收机电路的功率降低方案，并且屏蔽逻辑以屏蔽静噪接收机的输出。 此外，该提案利用计数器来计数各种超时条件。 因此，静噪接收器消耗较少的功率，并且可以断电或周期性地允许轮询。

公开(公告)号：US20080046628A1

公开(公告)日：2008-02-21

申请号：US11618372

申请日：2006-12-29

申请人： Mikal Hunsaker ,  Travis Schluessler ,  Thomas Slaight ,  David Hines

发明人： Mikal Hunsaker ,  Travis Schluessler ,  Thomas Slaight ,  David Hines

IPC分类号： G06F13/36

CPC分类号： G06F13/423

摘要： A management controller configured to generate and transmit transport layer packets to send management messages to a plurality of recipients managed by the management controller, co-disposed on the same computing platform, is disclosed and described herein. The managed recipients may be coupled to the management controller via buses of different bus types. The management controller is configured to logically address the managed recipients, to automatically split a management message over multiple packets when constrained by data bandwidth of a bus of a particular bus type, or to appropriately format the transport layer packets for the different buses of different bus types.

摘要翻译： 一种管理控制器，被配置为生成和发送传输层分组以将共同设置在同一计算平台上的管理控制器管理的多个接收者发送管理消息。 管理的接收者可以通过不同总线类型的总线耦合到管理控制器。 管理控制器被配置为逻辑地寻址受管理的接收者，当被特定总线类型的总线的数据带宽约束时，通过多个分组自动分割管理消息，或者适当地格式化不同总线的不同总线的传输层分组 类型。

公开(公告)号：US20060090014A1

公开(公告)日：2006-04-27

申请号：US10975132

申请日：2004-10-27

申请人： Kar Wong ,  Mikal Hunsaker ,  Prasanna Shah

发明人： Kar Wong ,  Mikal Hunsaker ,  Prasanna Shah

IPC分类号： G06F3/00

CPC分类号： G06F13/423

摘要： Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.

摘要翻译： 外围组件互连（PCI）Express的事务层链接处理。 初始化I / O控制器的输入/输出（I / O）控制器端口和设备的设备端口之间的链接，其中链路包括物理层，数据链路层和事务层。 在没有软件干预的情况下，在数据链路关闭状态之后，事务层被恢复。

公开(公告)号：US20050289278A1

公开(公告)日：2005-12-29

申请号：US10877560

申请日：2004-06-24

申请人： Thian Tan ,  Vui Liew ,  Mikal Hunsaker

发明人： Thian Tan ,  Vui Liew ,  Mikal Hunsaker

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4027 ,  G06F2213/0026

摘要： Method and apparatus for programmable completion tracking logic to support multiple virtual channels. In one embodiment, the apparatus includes a controller having the programmable completion tracking logic for supporting multiple virtual channels. In one embodiment, a completion tracking queue is programmable to provide a predetermined number of entries to store upstream non-posted (NP) read request information corresponding to a virtual channel from a plurality of virtual channels supported by the controller. In one embodiment, the predetermined number of entries are shared among the plurality of virtual channels according to a minimum entry value and a maximum entry value defined for each respective virtual channel. Other embodiments are described and claimed.

摘要翻译： 用于可编程完成跟踪逻辑以支持多个虚拟通道的方法和装置。 在一个实施例中，该装置包括具有用于支持多个虚拟通道的可编程完成跟踪逻辑的控制器。 在一个实施例中，完成跟踪队列是可编程的，以提供预定数量的条目以存储来自由控制器支持的多个虚拟通道对应于虚拟通道的上游非发布（NP）读取请求信息。 在一个实施例中，根据为每个相应虚拟频道定义的最小入口值和最大入口值，在多个虚拟信道中共享预定数量的条目。 描述和要求保护其他实施例。