公开(公告)号：US4525848A

公开(公告)日：1985-06-25

申请号：US500461

申请日：1983-06-02

申请人： Raymond W. Simpson

发明人： Raymond W. Simpson

IPC分类号： H04L7/033 ,  H04L25/48 ,  H04L25/49 ,  H03D3/22

CPC分类号： H04L25/4904 ,  H04L7/0331 ,  H04L7/0337

摘要： A circuit for generating a timing signal in a Manchester decoder comprises an oscillator 10, a frequency divider 14 for dividing signals derived from the oscillator, and a comparator 18 for comparing the times of transitions in the output signal of the divider with transitions in input Manchester data. To form a digital phase locked loop, gates 12 and 16 are provided for selectively adding a pulse to and subtracting a pulse from the pulses applied to the divider 14 by the oscillator 10 in dependence upon the relative timing determined by the comparator 18, in such manner as to lock the phase of the output signal of the divider onto the phase of the Manchester data. A squelch circuit is also provided for inhibiting phase control by the comparator 18 in response to a drop in signal strength of the received signal containing the Manchester data.

摘要翻译： 用于在曼彻斯特解码器中产生定时信号的电路包括振荡器10，用于分频从振荡器导出的信号的分频器14，以及比较器18，用于将分频器的输出信号中的转换时间与输入曼彻斯特 数据。 为了形成数字锁相环，提供了门12和16，用于根据由比较器18确定的相对定时，选择性地将脉冲加到由振荡器10施加到除法器14的脉冲中并从其中减去脉冲， 以将分频器的输出信号的相位锁定在曼彻斯特数据的相位上。 还提供了一种静噪电路，用于响应于包含曼彻斯特数据的接收信号的信号强度下降，禁止比较器18的相位控制。